| Title | Statistical Analysis of BTI in the Presence of Process-induced Voltage and Temperature Variations |
| Author | *Farshad Firouzi, Saman Kiamehr, Mehdi B. Tahoori (Karlsruhe Institute of Technology, Germany) |
| Page | pp. 594 - 600 |
| Keyword | NBTI, PBTI, PVT, Reliability, Timing analysis |
| Abstract | In nano-scale regime, there are various sources of uncertainty
and unpredictability of VLSI designs such as transistor aging
mainly due to Bias Temperature Instability (BTI) as well as Process-Voltage-Temperature (PVT) variations. BTI exponentially varies by
temperature and the actual supply voltage seen by the transistors
within the chip which are functions of leakage power. Leakage power is
strongly impacted by PVT and BTI which in turn results in thermal-voltage
variations. Hence, neglecting one or some of these aspects can
lead to a considerable inaccuracy in the estimated BTI-induced delay
degradation. However, a holistic approach to tackle all these issues and
their interdependence is missing. In this paper, we develop an analytical
model to predict the probability density function and covariance of
temperatures and voltage droops of a die in the presence of the BTI
and process variation. Based on this model, we propose a statistical
method that characterizes the life-time of the circuit affected by BTI
in the presence of process-induced temperature-voltage variations. We
observe that for benchmark circuits, treating each aspect independently
and ignoring their intrinsic interactions results in 16% over-design,
translating to unnecessary yield and performance loss. |
| Slides |
| Title | CLASS: Combined Logic and Architectural Soft Error Sensitivity Analysis |
| Author | *Mojtaba Ebrahimi, Liang Chen (Karlsruhe Institute of Technology, Germany), Hossein Asadi (Sharif University of Technology, Iran), Mehdi B. Tahoori (Karlsruhe Institute of Technology, Germany) |
| Page | pp. 601 - 607 |
| Keyword | Reliability Analysis, Soft Error, ACE, Error Propagation, Markov Chains |
| Abstract | With continuous technology downscaling, the rate of radiation induced soft errors is rapidly increasing. Fast and accurate soft error vulnerability analysis in early design stages plays an important
role in cost-effective reliability improvement. However, existing solutions are suitable for either regular (a.k.a address-based such as memory hierarchy) or irregular (random logic such as functional units and control logic) structures, failing to provide an accurate system level analysis. In this paper, we propose a hybrid approach integrating architecture-level and logic-level techniques to accurately estimate the vulnerability of all regular and irregular structures within a microprocessor. It carefully handles error propagation and masking scenarios among these structures. We have evaluated the vulnerability of the OR1200 processor using the
proposed approach. Comparison with statistical fault injection shows
an average inaccuracy of less than 5% with five orders of magnitude
improvement in runtime. |
| Slides |
| Title | Application Specified Soft Error Failure Rate Analysis using Sequential Equivalence Checking Techniques |
| Author | *Tun Li, Dan Zhu, Sikun Li, Yang Guo (National University of Defense Technology, China) |
| Page | pp. 608 - 613 |
| Keyword | Soft-error, Failure rate analysis, Sequential equivalence checking, Application |
| Abstract | Soft errors have become a critical challenge as a
result of technology scaling. However, to evaluate the influence
of soft errors in flip-flop (FF) on the failure of circuit is a hard
verification problem. Here, we proposed a novel flip-flop soft
error failure rate analysis methodology using sequential
equivalence checking (SEC) and taking the application
behaviors into consideration, which combines the advantage of
formal techniques based approaches in completeness and the
advantage of application behaviors in accuracy in
differentiating vulnerability of FFs. As a result, all the FFs in a
circuit are sorted by their failure rates and designers can use
this information to perform optimal hardening of selected
sequential components against soft errors. Experimental
results on an implementation of a SpaceWire end node and the
set of the largest ISCAS’89 benchmark sequential circuits
demonstrate the efficiency of our approach. Case study on an
instruction decoder of a practical 32 bits microprocessor shows
the applicable of our methodology. |
| Slides |
| Title | An Adaptive Current-Threshold Determination for IDDQ Testing Based on Bayesian Process Parameter Estimation |
| Author | *Michihiro Shintani, Takashi Sato (Graduate School of Informatics, Kyoto University, Japan) |
| Page | pp. 614 - 619 |
| Keyword | IDDQ testing, Statistical leakage current analysis, Bayes' Theorem |
| Abstract | Application of IDDQ testing to LSIs fabricated using advanced process technology is becoming increasingly difficult due to large variability of scaled devices. In this paper, we propose a novel technique that adaptively determines per-chip current-threshold for IDDQ testing to enhance test accuracy. In the proposed technique, process condition of a chip and fault sensitization vector are first estimated based on measured IDDQ currents through Bayesian inference. Then, using the estimated process condition, a statistical distribution of the leakage current for each test pattern is calculated and suitable current-threshold is determined by the distribution. Simulation experiments demonstrate that the proposed technique can successfully detect a very small leakage fault, down to 2% of the nominal IDDQ current with the test escape ratio of 3.1%. |
| Slides |