Title | VFCC: A Verification Framework of Cache Coherence using Parallel Simulation |
Author | *Qiaoli Xiong, Jiangfang Yi, Tianbao Song, Zichao Xie, Dong Tong (Peking Univ., China) |
Page | pp. 705 - 710 |
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Title | A Computational Model for SAT-based Verification of Hardware-Dependent Low-Level Embedded System Software |
Author | *Bernard Schmidt, Carlos Villarraga (Univ. of Kaiserslautern, Germany), Jörg Bormann (-, Germany), Dominik Stoffel, Markus Wedler, Wolfgang Kunz (Univ. of Kaiserslautern, Germany) |
Page | pp. 711 - 716 |
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Title | Reviving Erroneous Stability-based Clock-Gating using Partial Max-SAT |
Author | Bao Le, *Dipanjan Sengupta, Andreas Veneris (Univ. of Toronto, Canada) |
Page | pp. 717 - 722 |
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Slides |
Title | Simplification of C-RTL Equivalent Checking for Fused Multiply Add Unit using Intermediate Models |
Author | *Bin Xue, Prosenjit Chatterjee (Nvidia Corp, U.S.A.), Sandeep K. Shukla (Virginia Tech, U.S.A.) |
Page | pp. 723 - 728 |
Detailed information (abstract, keywords, etc) | |
Slides |