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The 18th Asia and South Pacific Design Automation Conference

Session 8D  Advances in Simulation and Formal Verification
Time: 13:40 - 15:40 Friday, January 25, 2013
Chairs: Miroslav Velev (Aries Design Automation, U.S.A.), Andreas Veneris (Univ. of Toronto, Canada)

8D-1 (Time: 13:40 - 14:10)
TitleVFCC: A Verification Framework of Cache Coherence using Parallel Simulation
Author*Qiaoli Xiong, Jiangfang Yi, Tianbao Song, Zichao Xie, Dong Tong (Peking Univ., China)
Pagepp. 705 - 710
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8D-2 (Time: 14:10 - 14:40)
TitleA Computational Model for SAT-based Verification of Hardware-Dependent Low-Level Embedded System Software
Author*Bernard Schmidt, Carlos Villarraga (Univ. of Kaiserslautern, Germany), Jörg Bormann (-, Germany), Dominik Stoffel, Markus Wedler, Wolfgang Kunz (Univ. of Kaiserslautern, Germany)
Pagepp. 711 - 716
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8D-3 (Time: 14:40 - 15:10)
TitleReviving Erroneous Stability-based Clock-Gating using Partial Max-SAT
AuthorBao Le, *Dipanjan Sengupta, Andreas Veneris (Univ. of Toronto, Canada)
Pagepp. 717 - 722
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8D-4 (Time: 15:10 - 15:40)
TitleSimplification of C-RTL Equivalent Checking for Fused Multiply Add Unit using Intermediate Models
Author*Bin Xue, Prosenjit Chatterjee (Nvidia Corp, U.S.A.), Sandeep K. Shukla (Virginia Tech, U.S.A.)
Pagepp. 723 - 728
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