| Title | Stable Backward Reachability Correction for PLL Verification with Consideration of Environmental Noise Induced Jitter |
| Author | Yang Song, Haipeng Fu, *Hao Yu (Nanyang Technological University, Singapore), Guoyong Shi (Shanghai Jiao Tong University, China) |
| Page | pp. 755 - 760 |
| Keyword | Analog/RF system verification, Reachability analysis, PLL jitter |
| Abstract | It is unknown to perform efficient PLL system-level verification with consideration of jitter induced by substrate or power-supply noise. With the consideration of nonlinear phase noise macromodel, this paper introduces a forward reachability analysis with stable backward correction for PLL system-level verification with jitter. By refining initial state of PLL through backward correction, one can perform an efficient PLL verification to automatically adjust the locking range with consideration of environmental noise induced jitter. Moreover, to overcome the unstable nature during backward correction, a stability calibration is introduced in this paper to limit error. To validate our method, the proposed approach is applied to verify a number of PLL designs including single-LC or coupled-LC oscillators described by system-level behavioral model with jitter. Experimental results show that our forward reachability analysis with backward correction can succeed in reaching the adjusted locking range by correcting initial states in presence of environmental noise induced jitter. |
| Slides | |
| Title | Performance Bound and Yield Analysis for Analog Circuits under Process Variations |
| Author | Xue-Xin Liu (University of California, Riverside, U.S.A.), Adolfo Adair Palma-Rodriguez, Santiago Rodriguez-Chavez (Institute of Astrophysics, Optics, and Electronics, Mexico), *Sheldon X.-D. Tan (University of California, Riverside, U.S.A.), Esteban Tlelo-Cuautle (Institute of Astrophysics, Optics, and Electronics, Mexico), Yici Cai (Tsinghua University, China) |
| Page | pp. 761 - 766 |
| Keyword | bound analysis, variation, yield, optimization, symbolic analysis |
| Abstract | Yield estimation for analog integrated circuits are crucial for analog circuit design and optimization in the presence of process variations. In this paper, we present a novel analog yield estimation method based on performance bound analysis technique in frequency domain. The new method first derives the transfer functions of linear (or linearized) analog circuits via a graph-based symbolic analysis method. Then frequency response bounds of the transfer functions in terms of magnitude and phase are obtained by a nonlinear constrained optimization technique. To predict yield rate, bound information are employed to calculate Gaussian distribution functions. Experimental results show that the new method can achieve similar accuracy while delivers 20 times speedup over Monte Carlo simulation of HSPICE on some typical analog circuits. |
| Slides | |
| Title | Local Approximation Improvement of Trajectory Piecewise Linear Macromodels through Chebyshev Interpolating Polynomials |
| Author | Muhammad Umer Farooq, *Likun Xia (Universiti Teknologi PETRONAS, Malaysia) |
| Page | pp. 767 - 772 |
| Keyword | Chebyshev polynomial, Taylor polynomial, State space (SS) |
| Abstract | We introduce the concept of 2Dimensional (2D) scalability of trajectory piecewise linear (TPWL) macromodels through the exploitation of Chebyshev interpolating polynomials in each piecewise region. The goal of 2D scalability is to improve the local approximation properties of TPWL macromodels. Horizontal scalability is achieved through the reduction of number of linearization points along the trajectory; vertical scalability is obtained by extending the scope of macromodel to predict the response of a nonlinear system for inputs far from training trajectory. In this way more efficient macromodels are obtained in terms of simulation speed up of complex nonlinear systems. We provide the implementation details and illustrate the 2D scalability concept with an example using nonlinear transmission line. |