| Title | Range and Bitmask Analysis for Hardware Optimization in High-Level Synthesis |
| Author | *Marcel Gort, Jason H. Anderson (University of Toronto, Canada) |
| Page | pp. 773 - 779 |
| Keyword | High level synthesis, Range analysis, FPGA, Compiler, LLVM |
| Abstract | We consider how bit-level representations of variables in HLS can be used to optimize hardware. Range and bitmask based analyses are considered separately and in tandem, where range analysis pre-determines min/max ranges for variables in order to minimize the hardware that uses those variables and bitmask analysis characterizes individual bits within a word as either constants (1 or 0), sign bits, or unknowns, which may also permit hardware to be eliminated. Static compiler-based analysis is contrasted with dynamic profiling-based analysis in terms of their potential to impact area and speed of HLS-generated hardware. Results show optimizations in HLS based on static analysis reduce circuit area by 9%, while those based on dynamic analysis provide 34% area reduction. |
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| Title | A Gradual Scheduling Framework for Problem Size Reduction and Cross Basic Block Parallelism Exploitation in High-level Synthesis |
| Author | *Hongbin Zheng, Qingrui Liu, Junyi Li, Dihu Chen, Zixin Wang (Sun Yet-sen University, China) |
| Page | pp. 780 - 786 |
| Keyword | High-level synthesis, Electronic design automation and methodology, Scheduling |
| Abstract | In High-level Synthesis (HLS), scheduling has a critical impact on the quality of hardware implementation. However, the schedules of different operations are actually having unequal impacts on the Quality of Result. Based on this fact, we propose a novel scheduling framework, which is able to schedule the operations separately according their significance to Quality of Result, to avoid wasting the computational effort on noncritical operations. Furthermore, the proposed framework supports global code motion, which helps to improve the speed performance of the hardware implementation by distributing the execution time of operations across the their parent BB. |
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| Title | Implementing Microprocessors from Simplified Descriptions |
| Author | *Nikhil A. Patil, Derek Chiou (University of Texas at Austin, U.S.A.) |
| Page | pp. 787 - 793 |
| Keyword | high-level synthesis, Bluespec, Microcode, Processors |
| Abstract | Despite the proliferation of high-level synthesis tools, hardware description of microprocessors remains complex. We argue that much of the incidental complexity can be relieved by untangling the description into separate functional and microarchitectural components. Such an untangling can be achieved using a high-level microcode compiler that can generate not only microcode, but also the micro-instruction format and the interpretations of each control bit. Simplifying hardware description will help the designer make better design-space trade-offs, and close the design and verification loop faster. This paper takes the reader through an implementation of a simple Y86 processor to qualitatively illustrate the complexity reduction from the untangling. |
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| Title | Application-Specific Fault-Tolerant Architecture Synthesis for Digital Microfluidic Biochips |
| Author | *Mirela Alistar, Paul Pop, Jan Madsen (Denmark Technical University, Denmark) |
| Page | pp. 794 - 800 |
| Keyword | digital microfluidics biochips, CAD tools, architecture synthesis, fault tolerant |
| Abstract | Microfluidic-based biochips are replacing the conventional biochemical analyzers, and are able to integrate on-chip all the necessary functions for biochemical analysis using microfluidics. The digital microfluidic biochips are based on the manipulation of liquids not as a continuous flow, but as discrete droplets on an array of electrodes. Microfluidic operations, such as transport, mixing, split, are performed on this array by routing the corresponding droplets on a series of electrodes. Researchers have proposed several approaches for the synthesis of digital microfluidic biochips. All previous work assumes that the biochip architecture is given, and most approaches consider a rectangular shape for the electrode array. However, non-regular application-specific architectures are common in practice. Hence, in this paper, we propose an approach to the application-specific architecture synthesis. Our approach can also help the designer to increase the yield by introducing redundant electrodes to tolerate permanent faults. The proposed architecture synthesis algorithm has been evaluated using several benchmarks. |
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