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The 19th Asia and South Pacific Design Automation Conference

Session 1S  Special Session: Normally-Off Computing: Towards Zero Stand-by Power Management
Time: 10:40 - 12:20 Tuesday, January 21, 2014
Location: Room 302
Organizer: Hiroshi Nakamura (University of Tokyo, Japan)

1S-1 (Time: 10:40 - 11:05)
Title(Invited Paper) Normally-Off Computing Project : Challenges and Opportunities
Author*Hiroshi Nakamura, Takashi Nakada, Shinobu Miwa (The University of Tokyo, Japan)
Pagepp. 1 - 5
Keywordnormally-off, non-volatile memory, power gating
AbstractNormally-Off is a way of computing which aggressively powers off components of computer systems when they need not to operate. Simple power gating cannot fully take the chances of power reduction because volatile memories lose data when power is turned off. Recently, new non-volatile memories (NVMs) have appeared. High attention has been paid to normally-off computing using these NVMs. In this paper, its expectation and challenges are addressed with a brief introduction of our project started in 2011.
Slides

1S-2 (Time: 11:05 - 11:30)
Title(Invited Paper) Novel Nonvolatile Memory Hierarchies to Realize "Normally-Off Mobile Processors"
Author*Shinobu Fujita, Kumiko Nomura, Hiroki Noguchi, Susumu Takeda, Keiko Abe (Toshiba Corporation, Japan)
Pagepp. 6 - 11
KeywordSTT-MRAM, Normally-off computer, Normally-off processor, mobile processor, nonvolatile memory
AbstractThis paper presents novel processor architecture for HP-processor with nonvolatile/volatile hybrid cache memory. By simulations of high-performance (HP)-processor using MTJs, it has been clarified that total power of the HP-processor using perpendicular-(p-)STT-MRAM can be reduced by over 90 % with little degradation of processor performance. The presented architecture with nonvolatile memory hierarchy will realize the “normally-off computers”.
Slides

1S-3 (Time: 11:30 - 11:55)
Title(Invited Paper) Normally-Off MCU Architecture for Low-Power Sensor Node
Author*Masanori Hayashikoshi, Yohei Sato, Hiroshi Ueki, Hiroyuki Kawai, Toru Shimizu (Renesas Electronics Corporation, Japan)
Pagepp. 12 - 16
KeywordNormally-off, Low-power, Microcontroller, MCU
AbstractThe production volume of sensor nodes is much increased with the development of cyber-physical systems. Therefore, it becomes important how to reduce the power consumption of huge sensor nodes. In this work, normally-off architecture of microcontroller for future low-power sensor node is proposed. To realize true low-power effects with normally-off computing technology, a co-design of hardware and software technology is much important. In this work, the power consumption of sensor nodes is possible to reduce of around 70%.
Slides

1S-4 (Time: 11:55 - 12:20)
Title(Invited Paper) Normally-Off Technologies for Healthcare Appliance
Author*Shintaro Izumi, Hiroshi Kawaguchi, Yoshimoto Masahiko (Kobe University, Japan), Yoshikazu Fujimori (Rohm, Japan)
Pagepp. 17 - 20
KeywordECG, Heart rate, Healthcare
AbstractBattery mass and power consumption of wearable system must be reduced because the key factors affecting wearable system usability are miniaturization and weight reduction. This report describes a wearable biosignal monitoring system using normally-off technologies to minimize the power consumption. Especially we focused on daily-life monitoring and electrocardiograph processor. Our system employs FeRAM and Near Field Communication (NFC). A robust heart rate monitor and Cortex M0 core are used to on-node processing for logging data reduction.
Slides