| Title | A Comprehensive and Accurate Latency Model for Network-on-Chip Performance Analysis |
| Author | *Zhiliang Qian (Hong Kong Univ. of Science and Tech., Hong Kong), Da-cheng Juan (Carnegie Mellon Univ., U.S.A.), Paul Bogdan (Univ. of Southern California, U.S.A.), Chi-Ying Tsui (Hong Kong Univ. of Science and Tech., Hong Kong), Diana Marculescu, Radu Marculescu (Carnegie Mellon Univ., U.S.A.) |
| Page | pp. 323 - 328 |
| Detailed information (abstract, keywords, etc) | |
| Slides | |
| Title | A Low-Latency Asynchronous Interconnection Network with Early Arbitration Resolution |
| Author | Georgios Faldamis (Cavium, U.S.A.), *Weiwei Jiang (Columbia Univ., U.S.A.), Gennette Gill (D.E. Shaw Research, U.S.A.), Steven M. Nowick (Columbia Univ., U.S.A.) |
| Page | pp. 329 - 336 |
| Detailed information (abstract, keywords, etc) | |
| Slides | |
| Title | A Vertically Integrated and Interoperable Multi-Vendor Synthesis Flow for Predictable NoC Design in Nanoscale Technologies |
| Author | *Alberto Ghiribaldi, Herve Tatenguem Fankem (Univ. of Ferrara, Italy), Federico Angiolini (iNoCs, Switzerland), Mikkel Stensgaard, Tobias Bjerregaard (Teklatech, Denmark), Davide Bertozzi (Univ. of Ferrara, Italy) |
| Page | pp. 337 - 342 |
| Detailed information (abstract, keywords, etc) | |
| Slides | |
| Title | Fuzzy Flow Regulation for Network-on-Chip Based Chip Multiprocessors Systems |
| Author | *Yuan Yao, Zhonghai Lu (Royal Inst. of Tech., Sweden) |
| Page | pp. 343 - 348 |
| Detailed information (abstract, keywords, etc) | |
| Slides | |
| Title | Adjustable Contiguity of Run-Time Task Allocation in Networked Many-Core Systems |
| Author | *Mohammad Fattah, Pasi Liljeberg, Juha Plosila, Hannu Tenhunen (Univ. of Turku, Finland) |
| Page | pp. 349 - 354 |
| Detailed information (abstract, keywords, etc) | |
| Slides | |