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The 19th Asia and South Pacific Design Automation Conference

Session 5A  Simulation and Modeling
Time: 13:50 - 15:30 Wednesday, January 22, 2014
Location: Room 300
Chairs: Atushi Ike (Fujitsu Labs., Japan), Yuichi Nakamura (NEC, Japan)

5A-1 (Time: 13:50 - 14:15)
TitleAmphisbaena: Modeling Two Orthogonal Ways to Hunt on Heterogeneous Many-Cores
Author*Jun Ma, Guihai Yan, Yinhe Han, Xiaowei Li (Chinese Academy of Sciences, China)
Pagepp. 394 - 399
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5A-2 (Time: 14:15 - 14:40)
TitleCo-Simulation Framework for Streamlining Microprocessor Development on Standard ASIC Design Flow
Author*Tomoyuki Nakabayashi, Tomoyuki Sugiyama, Takahiro Sasaki (Mie Univ., Japan), Eric Rotenberg (North Carolina State Univ., U.S.A.), Toshio Kondo (Mie Univ., Japan)
Pagepp. 400 - 405
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5A-3 (Time: 14:40 - 15:05)
TitleAnnotation and Analysis Combined Cache Modeling for Native Simulation
AuthorRongjie Yan (Chinese Academy of Sciences, China), *De Ma (Hangzhou Dianzi Univ., China), Kai Huang, Xiaoxu Zhang, Siwen Xiu (Zhejiang Univ., China)
Pagepp. 406 - 411
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5A-4 (Time: 15:05 - 15:30)
TitleA Scorchingly Fast FPGA-Based Precise L1 LRU Cache Simulator
Author*Josef Schneider, Jorgen Peddersen, Sri Parameswaran (Univ. of New South Wales, Australia)
Pagepp. 412 - 417
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