| Title | No△:Leveraging Delta Compression for End-to-End Memory Access in NoC Based Multicores |
| Author | *Jia Zhan, Matt Poremba (Pennsylvania State Univ., U.S.A.), Yi Xu (AMD Research, China), Yuan Xie (AMD, China/Pennsylvania State Univ., U.S.A.) |
| Page | pp. 586 - 591 |
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| Slides | |
| Title | DPA: A Data Pattern Aware Error Prevention Technique for NAND Flash Lifetime Extension |
| Author | Jie Guo, Zhijie Chen (Univ. of Pittsburgh, U.S.A.), Danghui Wang (Northwestern Polytechnical Univ., China), Zili Shao (Hong Kong Polytechnic Univ., Hong Kong), *Yiran Chen (Univ. of Pittsburgh, U.S.A.) |
| Page | pp. 592 - 597 |
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| Title | Scattered Refresh: An Alternative Refresh Mechanism to Reduce Refresh Cycle Time |
| Author | *T. Venkata Kalyan, Ravi Kasha, Madhu Mutyam (Indian Inst. of Tech. - Madras, India) |
| Page | pp. 598 - 603 |
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| Slides | |
| Title | A Read-Write Aware DRAM Scheduling for Power Reduction in Multi-Core Systems |
| Author | *Chih-Yen Lai, Gung-Yu Pan, Hsien-Kai Kuo (National Chiao Tung Univ., Taiwan), Jing-Yang Jou (National Central Univ./National Chiao Tung Univ., Taiwan) |
| Page | pp. 604 - 609 |
| Detailed information (abstract, keywords, etc) | |
| Slides | |
| Title | A Coherent Hybrid SRAM and STT-RAM L1 Cache Architecture for Shared Memory Multicores |
| Author | *Jianxing Wang, Yenni Tim, Weng-Fai Wong, Zhong-Liang Ong (National Univ. of Singapore, Singapore), Zhenyu Sun, Hai (Helen) Li (Univ. of Pittsburgh, U.S.A.) |
| Page | pp. 610 - 615 |
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