The 19th Asia and South Pacific Design Automation Conference
Technical Program

Remark: The presenter of each paper is marked with "*".

Technical Program: SIMPLE version DETAILED version with abstract

Author Index: HERE

Session Schedule

Tuesday, January 21, 2014

Room 302	Room 300	Room 301	Room 303
1K (Room 300) Opening & Keynote I 8:30 - 10:00
Break 10:00 - 10:40
1S Special Session: Normally-Off Computing: Towards Zero Stand-by Power Management 10:40 - 12:20	1A University Design Contest 10:40 - 12:20	1B Planning and Placement for Design Closure and Manufacturability 10:40 - 12:20	1C Circuit, Architecture, and System for Emerging Technologies 10:40 - 12:20
Lunch Break 12:20 - 13:50
2S Special Session: EDA for Energy 13:50 - 15:30	2A Distributed and Mixed-Criticality Real-Time Systems 13:50 - 15:30	2B Advanced Patterning for Advanced Layout 13:50 - 15:30	2C Timing-Driven Design, Modeling, and Optimization 13:50 - 15:30
Break 15:30 - 15:50
3S Special Session: Neuron Inspired Computing using Nanotechnology 15:50 - 17:30	3A Synthesis and Exploration Techniques for Computing Platforms 15:50 - 17:30	3B Advances in Microfluidic Biochips 15:50 - 17:30	3C Advanced Modeling and Simulation Techniques for Analog/Mixed-Signal Circuits 15:50 - 17:30

Wednesday, January 22, 2014

Room 302	Room 300	Room 301	Room 303
2K (Room 300) Keynote II 8:30 - 9:30
Break 9:30 - 10:10
4S Special Session: Design Automation Methods for Highly-Complex Multimedia Systems 10:10 - 12:15	4A System-Level Thermal and Power Optimization Techniques 10:10 - 12:15	4B Emerging Techniques for Future NoC 10:10 - 12:15	4C Emerging Applications 10:10 - 12:15
Lunch Break 12:15 - 13:50
5S Special Session: Billion Chips of Trillion Transistors 13:50 - 15:30	5A Simulation and Modeling 13:50 - 15:30	5B Reliability Analysis and Enhencement 13:50 - 15:30	5C Variational Design Techniques for Analog/Mixed-Signal Circuits 13:50 - 15:30
Break 15:30 - 15:50
6S Special Session: Overcoming Major Silicon Bottlenecks: Variability, Reliability, Validation and Debug 15:50 - 17:30	6A Synthesis of Quantum Circuits and Adaptive Logic 15:50 - 17:30	6B Contemporary Routing 15:50 - 17:30	6C Power Supply Noise Aware Design Optimization 15:50 - 17:30
Break 17:30 - 18:30
BK (Flower Field Hall, Gardens by the Bay) Banquet & Banquet Keynote 18:30 - 21:00

Thursday, January 23, 2014

Room 302	Room 300	Room 301	Room 303
3K (Room 300) Keynote III 8:30 - 9:30
Break 9:30 - 10:10
7S Special Session: Brain Like Computing: Modelling, Technology, and Architecture 10:10 - 12:15	7A Power and Life Time Issues of Memory Subsystem 10:10 - 12:15	7B Advances in High-Level and Logic Synthesis 10:10 - 12:15	7C Advanced Test Solutions 10:10 - 12:15
Lunch Break 12:15 - 13:50
8S Special Session: Design Flow for Integrated Circuits using Magnetic Tunnel Junction Switched by Spin Orbit Torque 13:50 - 15:30	8A Analysis, Optimization, and Scheduling for Multiprocessor Platforms 13:50 - 15:30	8B Advances in Formal Verification and Debugging 13:50 - 15:30	8C Advances in CAD Techniques for Signal Integrity 13:50 - 15:30
Break 15:30 - 15:50
9S Special Session: The Role of Photons in Harming or Increasing Security 15:50 - 17:30	9A System-Level Verification 15:50 - 17:30	9B Modeling and Evaluator for Emerging Technologies 15:50 - 17:30	9C Design and Simulation Toward Power and Temperature Awareness 15:50 - 17:30

List of Papers

Remark: The presenter of each paper is marked with "*".

Tuesday, January 21, 2014

Session 1K Opening & Keynote I
Time: 8:30 - 10:00 Tuesday, January 21, 2014
Location: Room 300
Chairs: Yong Lian (National Univ. of Singapore, Singapore), Yajun Ha (National Univ. of Singapore, Singapore)

1K-1 (Time: 9:00 - 10:00)

Title	(Keynote Address) All Programmable SOC FPGA for Networking and Computing in Big Data Infrastructure
Author	Ivo Bolsens (Senior VP and CTO, Xilinx, U.S.A.)
Detailed information (abstract, keywords, etc)

Session 1S Special Session: Normally-Off Computing: Towards Zero Stand-by Power Management
Time: 10:40 - 12:20 Tuesday, January 21, 2014
Location: Room 302
Organizer: Hiroshi Nakamura (Univ. of Tokyo, Japan)

1S-1 (Time: 10:40 - 11:05)

Title	(Invited Paper) Normally-Off Computing Project : Challenges and Opportunities
Author	*Hiroshi Nakamura, Takashi Nakada, Shinobu Miwa (Univ. of Tokyo, Japan)
Page	pp. 1 - 5
Detailed information (abstract, keywords, etc)
Slides

1S-2 (Time: 11:05 - 11:30)

Title	(Invited Paper) Novel Nonvolatile Memory Hierarchies to Realize "Normally-Off Mobile Processors"
Author	*Shinobu Fujita, Kumiko Nomura, Hiroki Noguchi, Susumu Takeda, Keiko Abe (Toshiba, Japan)
Page	pp. 6 - 11
Detailed information (abstract, keywords, etc)
Slides

1S-3 (Time: 11:30 - 11:55)

Title	(Invited Paper) Normally-Off MCU Architecture for Low-Power Sensor Node
Author	*Masanori Hayashikoshi, Yohei Sato, Hiroshi Ueki, Hiroyuki Kawai, Toru Shimizu (Renesas Electronics, Japan)
Page	pp. 12 - 16
Detailed information (abstract, keywords, etc)
Slides

1S-4 (Time: 11:55 - 12:20)

Title	(Invited Paper) Normally-Off Technologies for Healthcare Appliance
Author	*Shintaro Izumi, Hiroshi Kawaguchi, Yoshimoto Masahiko (Kobe Univ., Japan), Yoshikazu Fujimori (Rohm, Japan)
Page	pp. 17 - 20
Detailed information (abstract, keywords, etc)
Slides

Session 1A University Design Contest
Time: 10:40 - 12:20 Tuesday, January 21, 2014
Location: Room 300
Chair: Chun Huat Heng (National Univ. of Singapore, Singapore)

1A-1 (Time: 10:40 - 10:44)

Title	A Dual-Loop Injection-Locked PLL with All-Digital Background Calibration System for On-Chip Clock Generation
Author	*Wei Deng, Ahmed Musa, Teerachot Siriburanon, Masaya Miyahara, Kenichi Okada, Akira Matsuzawa (Tokyo Inst. of Tech., Japan)
Page	pp. 21 - 22
Detailed information (abstract, keywords, etc)
Slides

1A-2 (Time: 10:44 - 10:48)

Title	A 950µW 5.5-GHz Low Voltage PLL with Digitally-Calibrated ILFD and Linearized Varactor
Author	*Sho Ikeda, Tatsuya Kamimura, Sangyeop Lee, Hiroyuki Ito, Noboru Ishihara, Kazuya Masu (Tokyo Inst. of Tech., Japan)
Page	pp. 23 - 24
Detailed information (abstract, keywords, etc)
Slides

1A-3 (Time: 10:48 - 10:52)

Title	A Swing-Enhanced Current-Reuse Class-C VCO with Dynamic Bias Control Circuits
Author	*Teerachot Siriburanon, Wei Deng, Kenichi Okada, Akira Matsuzawa (Tokyo Inst. of Tech., Japan)
Page	pp. 25 - 26
Detailed information (abstract, keywords, etc)

1A-4 (Time: 10:52 - 10:56)

Title	Design of A High-Performance Millimeter-Wave Amplifier Using Specific Modeling
Author	Xiaojun Bi (National Univ. of Singapore/ASTAR, Singapore), Yongxin Guo (National Univ. of Singapore, Singapore/National Univ. of Singapore (Suzhou) Research Institute, China), M. Annamalai Arasu (ASTAR, Singapore), M. S. Zhnag (National Univ. of Singapore, Singapore), Yong Zhong Xiong, Minkyu Je (ASTAR, Singapore)
Page	pp. 27 - 28
Detailed information (abstract, keywords, etc)

1A-5 (Time: 10:56 - 11:00)

Title	A Multi-Mode Reconfigurable Analog Baseband with I/Q Calibration for GNSS Receivers
Author	*Zheng Song, Nan Qi, Baoyong Chi, Zhihua Wang (Tsinghua Univ., China)
Page	pp. 29 - 30
Detailed information (abstract, keywords, etc)
Slides

1A-6 (Time: 11:00 - 11:04)

Title	An 8b Extremely Area Efficient Threshold Configuring SAR ADC with Source Voltage Shifting Technique
Author	*Kentaro Yoshioka, Akira Shikata, Ryota Sekimoto, Tadahiro Kuroda, Hiroki Ishikuro (Keio Univ., Japan)
Page	pp. 31 - 32
Detailed information (abstract, keywords, etc)
Slides

1A-7 (Time: 11:04 - 11:08)

Title	A Single-Inductor 8-Channel Output DC-DC Boost Converter with Time-Limited Power Distribution Control and Single Shared Hysteresis Comparator
Author	*Jungmoon Kim, Chulwoo Kim (Korea Univ., Republic of Korea)
Page	pp. 33 - 34
Detailed information (abstract, keywords, etc)

1A-8 (Time: 11:08 - 11:12)

Title	A DC-DC Boost Converter with Variation Tolerant MPPT Technique and Efficient ZCS Circuit for Thermoelectric Energy Harvesting Applications
Author	*Jungmoon Kim, Minseob Shim, Junwon Jung, Heejun Kim, Chulwoo Kim (Korea Univ., Republic of Korea)
Page	pp. 35 - 36
Detailed information (abstract, keywords, etc)

1A-9 (Time: 11:12 - 11:16)

Title	7.3 Gb/s Universal BCH Encoder and Decoder for SSD Controllers
Author	*Hoyoung Yoo, Youngjoo Lee, In-Cheol Park (KAIST, Republic of Korea)
Page	pp. 37 - 38
Detailed information (abstract, keywords, etc)

1A-10 (Time: 11:16 - 11:20)

Title	A High-Speed and Low-Complexity Lens Distortion Correction Processor for Wide-Angle Cameras
Author	*Won-Tae Kim, Hui-Sung Jeong, Gwang-Ho Lee, Tae-Hwan Kim (Korea Aerospace Univ., Republic of Korea)
Page	pp. 39 - 40
Detailed information (abstract, keywords, etc)
Slides

Session 1B Planning and Placement for Design Closure and Manufacturability
Time: 10:40 - 12:20 Tuesday, January 21, 2014
Location: Room 301
Chairs: Shigetoshi Nakatake (Univ. of Kitakyushu, Japan), Hung-Ming Chen (National Chiao Tung Univ., Taiwan)

1B-1 (Time: 10:40 - 11:05)

Title	Analytical Placement of Mixed-Size Circuits for Better Detailed-Routability
Author	Shuai Li, *Cheng-Kok Koh (Purdue Univ., U.S.A.)
Page	pp. 41 - 46
Detailed information (abstract, keywords, etc)
Slides

1B-2 (Time: 11:05 - 11:30)

Title	Lithographic Defect Aware Placement Using Compact Standard Cells Without Inter-Cell Margin
Author	*Seongbo Shim, Yoojong Lee, Youngsoo Shin (KAIST, Republic of Korea)
Page	pp. 47 - 52
Detailed information (abstract, keywords, etc)
Slides

1B-3 (Time: 11:30 - 11:55)

Title	Structural Planning of 3D-IC Interconnects by Block Alignment
Author	*Johann Knechtel (Dresden Univ. of Tech., Germany), Evangeline F. Y. Young (Chinese Univ. of Hong Kong, Hong Kong), Jens Lienig (Dresden Univ. of Tech., Germany)
Page	pp. 53 - 60
Detailed information (abstract, keywords, etc)
Slides

1B-4 (Time: 11:55 - 12:20)

Title	Comprehensive Die-Level Assessment of Design Rules and Layouts
Author	Rani Ghaida (GLOBALFOUNDRIES, U.S.A.), Yasmine Badr (Univ. of California, Los Angeles, U.S.A.), Mukul Gupta (Qualcomm, U.S.A.), Ning Jin (GLOBALFOUNDRIES, U.S.A.), *Puneet Gupta (Univ. of California, Los Angeles, U.S.A.)
Page	pp. 61 - 66
Detailed information (abstract, keywords, etc)
Slides

Session 1C Circuit, Architecture, and System for Emerging Technologies
Time: 10:40 - 12:20 Tuesday, January 21, 2014
Location: Room 303
Chairs: Hai (Helen) Li (Univ. of Pittsburgh, U.S.A.), Danghui Wang (Northwestern Polytechnical Univ., China)

1C-1 (Time: 10:40 - 11:05)

Title	Prefetching Techniques for STT-RAM Based Last-Level Cache in CMP Systems
Author	Mengjie Mao (Univ. of Pittsburgh, U.S.A.), Guangyu Sun (Peking Univ., China), Yong Li, Alex K. Jones, *Yiran Chen (Univ. of Pittsburgh, U.S.A.)
Page	pp. 67 - 72
Detailed information (abstract, keywords, etc)
Slides

1C-2 (Time: 11:05 - 11:30)

Title	CNPUF: A Carbon Nanotube-based Physically Unclonable Function for Secure Low-Energy Hardware Design
Author	*Sven Tenzing Choden Konigsmark, Leslie K. Hwang, Deming Chen, Martin D. F. Wong (Univ. of Illinois, Urbana-Champaign, U.S.A.)
Page	pp. 73 - 78
Detailed information (abstract, keywords, etc)
Slides

1C-3 (Time: 11:30 - 11:55)

Title	3DCoB: A New Design Approach for Monolithic 3D Integrated Circuits
Author	*Hossam Sarhan, Sebastien Thuries, Olivier Billoint, Fabien Clermidy (CEA-LETI, France)
Page	pp. 79 - 84
Detailed information (abstract, keywords, etc)
Slides

1C-4 (Time: 11:55 - 12:20)

Title	Emulator-Oriented Tiny Processors for Unreliable Post-Silicon Devices: A Case Study
Author	*Yuko Hara-Azumi (Nara Inst. of Science and Tech./JST, PRESTO, Japan), Masaya Kunimoto, Yasuhiko Nakashima (NAIST, Japan)
Page	pp. 85 - 90
Detailed information (abstract, keywords, etc)

Session 2S Special Session: EDA for Energy
Time: 13:50 - 15:30 Tuesday, January 21, 2014
Location: Room 302
Organizer: Fadi Kurdahi (Univ. of California, Irvine, U.S.A.), Sani Nassif (IBM, U.S.A.), Mohammad Al Faruque (Univ. of California, Irvine, U.S.A.)

2S-1 (Time: 13:50 - 14:20)

Title	(Invited Paper) Applying VLSI EDA to Energy Distribution System Design
Author	*Sani Nassif, Gi-Joon Nam, Jerry Hayes (IBM, U.S.A.), Sani Fakhouri (Univ. of California, Irvine, U.S.A.)
Page	pp. 91 - 96
Detailed information (abstract, keywords, etc)

2S-2 (Time: 14:20 - 14:50)

Title	(Invited Paper) A Model-Based Design of Cyber-Physical Energy Systems
Author	Mohammad Abdullah Al Faruque, *Fereidoun Ahourai (Univ. of California, Irvine, U.S.A.)
Page	pp. 97 - 104
Detailed information (abstract, keywords, etc)

2S-3 (Time: 14:50 - 15:20)

Title	(Invited Paper) The Data Center as a Grid Load Stabilizer
Author	Hao Chen, Michael C. Caramanis, *Ayse K. Coskun (Boston Univ., U.S.A.)
Page	pp. 105 - 112
Detailed information (abstract, keywords, etc)
Slides

Session 2A Distributed and Mixed-Criticality Real-Time Systems
Time: 13:50 - 15:30 Tuesday, January 21, 2014
Location: Room 300
Chair: Muhammad Shafique (Karlsruhe Inst. of Tech., Germany)

2A-1 (Time: 13:50 - 14:15)

Title	Bounding Buffer Space Requirements for Real-Time Priority-Aware Networks
Author	Hany Kashif, *Hiren D. Patel (Univ. of Waterloo, Canada)
Page	pp. 113 - 118
Detailed information (abstract, keywords, etc)

2A-2 (Time: 14:15 - 14:40)

Title	Task- and Network-Level Schedule Co-Synthesis of Ethernet-Based Time-Triggered Systems
Author	*Licong Zhang, Dip Goswami, Reinhard Schneider, Samarjit Chakraborty (TU Munich, Germany)
Page	pp. 119 - 124
Detailed information (abstract, keywords, etc)
Slides

2A-3 (Time: 14:40 - 15:05)

Title	Service Adaptions for Mixed-Criticality Systems
Author	*Pengcheng Huang, Georgia Giannopoulou, Nikolay Stoimenov, Lothar Thiele (ETH Zurich, Switzerland)
Page	pp. 125 - 130
Detailed information (abstract, keywords, etc)
Slides

2A-4 (Time: 15:05 - 15:30)

Title	Efficient Feasibility Analysis of DAG Scheduling with Real-Time Constraints in the Presence of Faults
Author	*Xiaotong Cui, Jun Zhang, Kaijie Wu, Edwin Sha (Chongqing Univ., China)
Page	pp. 131 - 136
Detailed information (abstract, keywords, etc)
Slides

Session 2B Advanced Patterning for Advanced Layout
Time: 13:50 - 15:30 Tuesday, January 21, 2014
Location: Room 301
Chairs: Martin Wong (Univ. of Illinois, Urbana-Champaign, U.S.A.), Shigeki Nojima (Toshiba, Japan)

2B-1 (Time: 13:50 - 14:15)

Title	Flexible Packed Stencil Design with Multiple Shaping Apertures for E-Beam Lithography
Author	Chris Chu (Iowa State Univ., U.S.A.), *Wai-Kei Mak (National Tsing Hua Univ., Taiwan)
Page	pp. 137 - 142
Detailed information (abstract, keywords, etc)
Slides

2B-2 (Time: 14:15 - 14:40)

Title	Self-Aligned Double Patterning Layout Decomposition with Complementary E-Beam Lithography
Author	Jhih-Rong Gao, Bei Yu, *David Z. Pan (Univ. of Texas, Austin, U.S.A.)
Page	pp. 143 - 148
Detailed information (abstract, keywords, etc)
Slides

2B-3 (Time: 14:40 - 15:05)

Title	Fixing Double Patterning Violations with Look-Ahead
Author	*Sambuddha Bhattacharya, Subramanian Rajagopalan, Shabbir H Batterywala (Synopsys India Pvt., India)
Page	pp. 149 - 154
Detailed information (abstract, keywords, etc)
Slides

2B-4 (Time: 15:05 - 15:30)

Title	EUV-CDA: Pattern Shift Aware Critical Density Analysis for EUV Mask Layouts
Author	*Abde Ali Kagalwalla (Univ. of California, Los Angeles, U.S.A.), Michael Lam, Kostas Adam (Mentor Graphics, U.S.A.), Puneet Gupta (Univ. of California, Los Angeles, U.S.A.)
Page	pp. 155 - 160
Detailed information (abstract, keywords, etc)
Slides

Session 2C Timing-Driven Design, Modeling, and Optimization
Time: 13:50 - 15:30 Tuesday, January 21, 2014
Location: Room 303
Chairs: Mango Chia-Tso Chao (National Chiao Tung Univ., Taiwan), Tai-Chen Chen (National Central Univ., Taiwan)

2C-1 (Time: 13:50 - 14:15)

Title	Statistical Analysis of Random Telegraph Noise in Digital Circuits
Author	*Xiaoming Chen, Yu Wang (Tsinghua Univ., China), Yu Cao (Arizona State Univ., U.S.A.), Huazhong Yang (Tsinghua Univ., China)
Page	pp. 161 - 166
Detailed information (abstract, keywords, etc)
Slides

2C-2 (Time: 14:15 - 14:40)

Title	Semi-Analytical Current Source Modeling of FinFET Devices Operating in Near/Sub-Threshold Regime with Independent Gate Control and Considering Process Variation
Author	Tiansong Cui, Yanzhi Wang, Xue Lin, Shahin Nazarian, *Massoud Pedram (Univ. of Southern California, U.S.A.)
Page	pp. 167 - 172
Detailed information (abstract, keywords, etc)
Slides

2C-3 (Time: 14:40 - 15:05)

Title	2-SAT Based Linear Time Optimum Two-Domain Clock Skew Scheduling
Author	*Yukihide Kohira (Univ. of Aizu, Japan), Atsushi Takahashi (Tokyo Inst. of Tech., Japan)
Page	pp. 173 - 178
Detailed information (abstract, keywords, etc)

2C-4 (Time: 15:05 - 15:30)

Title	Power Minimization of Pipeline Architecture through 1-Cycle Error Correction and Voltage Scaling
Author	*Insup Shin (KAIST, Republic of Korea), Jae-Joon Kim (POSTECH, Republic of Korea), Youngsoo Shin (KAIST, Republic of Korea)
Page	pp. 179 - 184
Detailed information (abstract, keywords, etc)
Slides

Session 3S Special Session: Neuron Inspired Computing using Nanotechnology
Time: 15:50 - 17:30 Tuesday, January 21, 2014
Location: Room 302
Organizer: Kevin Cao (Arizona State Univ., U.S.A.), Sarma Vrudhula (Arizona State Univ., U.S.A.)

3S-1 (Time: 15:50 - 16:20)

Title	(Invited Paper) A Silicon Nanodisk Array Structure Realizing Synaptic Response of Spiking Neuron Models with Noise
Author	*Takashi Morie, Haichao Liang, Yilai Sun, Takashi Tohara (Kyushu Inst. of Tech., Japan), Makoto Igarashi, Seiji Samukawa (Tohoku Univ., Japan)
Page	pp. 185 - 190
Detailed information (abstract, keywords, etc)

3S-2 (Time: 16:20 - 16:50)

Title	(Invited Paper) Energy Efficient In-Memory Machine Learning for Data Intensive Image-Processing by Non-Volatile Domain-Wall Memory
Author	*Hao Yu, Yuhao Wang, Shuai Chen, Wei Fei (Nanyang Technological Univ., Singapore), Chuliang Weng, Junfeng Zhao, Zhulin Wei (Huawei Shannon Laboratory, China)
Page	pp. 191 - 196
Detailed information (abstract, keywords, etc)
Slides

3S-3 (Time: 16:50 - 17:20)

Title	(Invited Paper) Lessons from the Neurons Themselves
Author	*Louis Scheffer (Howard Hughes Medical Institute, U.S.A.)
Page	pp. 197 - 200
Detailed information (abstract, keywords, etc)
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Session 3A Synthesis and Exploration Techniques for Computing Platforms
Time: 15:50 - 17:30 Tuesday, January 21, 2014
Location: Room 300
Chairs: Sri Parameswaran (Univ. of New South Wales, Australia), Kyle Rupnow (Nanyang Technological Univ., Singapore)

3A-1 (Time: 15:50 - 16:15)

Title	Leveraging the Error Resilience of Machine-Learning Applications for Designing Highly Energy Efficient Accelerators
Author	*Zidong Du (Chinese Academy of Sciences, China), Avinash Lingamneni (Rice Univ., U.S.A.), Yunji Chen (Chinese Academy of Sciences, China), Krishna Palem (Rice Univ., U.S.A.), Olivier Temam (INRIA, France), Chengyong Wu (Chinese Academy of Sciences, China)
Page	pp. 201 - 206
Detailed information (abstract, keywords, etc)

3A-2 (Time: 16:15 - 16:40)

Title	ArISE: Aging-Aware Instruction Set Encoding for Lifetime Improvement
Author	*Fabian Oboril, Mehdi Tahoori (KIT, Germany)
Page	pp. 207 - 212
Detailed information (abstract, keywords, etc)
Slides

3A-3 (Time: 16:40 - 17:05)

Title	DRuiD: Designing Reconfigurable Architectures with Decision-Making Support
Author	*Giovanni Mariani (Univ. della Svizzera Italiana - ALaRI, Switzerland/Politecnico di Milano, Italy), Gianluca Palermo (Politecnico di Milano - DEIB, Italy), Roel Meeuws, Vlad-Mihai Sima (Delft Technical Univ., Netherlands), Cristina Silvano (Politecnico di Milano - DEIB, Italy), Koen Bertels (Delft Technical Univ., Netherlands)
Page	pp. 213 - 218
Detailed information (abstract, keywords, etc)
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3A-4 (Time: 17:05 - 17:30)

Title	Edit Distance Based Instruction Merging Technique to Improve Flexibility of Custom Instructions Toward Flexible Accelerator Design
Author	Hui Huang (Univ. of California, Los Angeles, U.S.A.), *Taemin Kim, Yatin Hoskote (Intel Labs, U.S.A.)
Page	pp. 219 - 224
Detailed information (abstract, keywords, etc)
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Session 3B Advances in Microfluidic Biochips
Time: 15:50 - 17:30 Tuesday, January 21, 2014
Location: Room 301
Chairs: Tsung-Yi Ho (National Cheng Kung Univ., Taiwan), Juinn-Dar Huang (National Chiao Tung Univ., Taiwan)

3B-1 (Time: 15:50 - 16:15)

Title	A Network-Flow-Based Optimal Sample Preparation Algorithm for Digital Microfluidic Biochips
Author	*Trung Anh Dinh, Shigeru Yamashita (Ritsumeikan Univ., Japan), Tsung-Yi Ho (National Cheng Kung Univ., Taiwan)
Page	pp. 225 - 230
Detailed information (abstract, keywords, etc)
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3B-2 (Time: 16:15 - 16:40)

Title	Exploring Speed and Energy Tradeoffs in Droplet Transport for Digital Microfluidic Biochips
Author	Johnathan Fiske, *Daniel Grissom, Philip Brisk (Univ. of California, Riverside, U.S.A.)
Page	pp. 231 - 237
Detailed information (abstract, keywords, etc)
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3B-3 (Time: 16:40 - 17:05)

Title	General Purpose Cross-Referencing Microfluidic Biochip with Reduced Pin-Count
Author	*Jackson Ho Chuen Yeung, Evangeline F.Y. Young (Chinese Univ. of Hong Kong, Hong Kong)
Page	pp. 238 - 243
Detailed information (abstract, keywords, etc)

3B-4 (Time: 17:05 - 17:30)

Title	Wash Optimization for Cross-Contamination Removal in Flow-Based Microfluidic Biochips
Author	Kai Hu (Duke Univ., U.S.A.), *Tsung-Yi Ho (National Cheng Kung Univ., Taiwan), Krishnendu Chakrabarty (Duke Univ., U.S.A.)
Page	pp. 244 - 249
Detailed information (abstract, keywords, etc)
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Session 3C Advanced Modeling and Simulation Techniques for Analog/Mixed-Signal Circuits
Time: 15:50 - 17:30 Tuesday, January 21, 2014
Location: Room 303
Chairs: Hao Yu (Nanyang Technological Univ., Singapore), Shi Guoyong (Shanghai Jiao Tong Univ., China)

3C-1 (Time: 15:50 - 16:15)

Title	ABCD-NL: Approximating Continuous Non-Linear Dynamical Systems Using Purely Boolean Models for Analog/Mixed-Signal Verification
Author	*Aadithya V. Karthik, Sayak Ray, Pierluigi Nuzzo, Alan Mishchenko, Robert Brayton, Jaijeet Roychowdhury (Univ. of California, Berkeley, U.S.A.)
Page	pp. 250 - 255
Detailed information (abstract, keywords, etc)

3C-2 (Time: 16:15 - 16:40)

Title	Toward Efficient Programming of Reconfigurable Radio Frequency (RF) Receivers
Author	*Jun Tao, Ying-Chih Wang, Minhee Jun, Xin Li, Rohit Negi, Tamal Mukherjee, Lawrence Pileggi (Carnegie Mellon Univ., U.S.A.)
Page	pp. 256 - 261
Detailed information (abstract, keywords, etc)
Slides

3C-3 (Time: 16:40 - 17:05)

Title	Efficient Matrix Exponential Method Based on Extended Krylov Subspace for Transient Simulation of Large-Scale Linear Circuits
Author	Quan Chen, *Wenhui Zhao, Ngai Wong (Univ. of Hong Kong, Hong Kong)
Page	pp. 262 - 266
Detailed information (abstract, keywords, etc)
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Wednesday, January 22, 2014

Session 2K Keynote II
Time: 8:30 - 9:30 Wednesday, January 22, 2014
Location: Room 300
Chair: Nagisa Ishiura (Kwansei Gakuin Univ., Japan)

2K-1 (Time: 8:30 - 9:30)

Title	(Keynote Address) Designing Analog Functions without Analog Transistors
Author	Georges Gielen (Katholieke Univ. Leuven, Belgium)
Detailed information (abstract, keywords, etc)

Session 4S Special Session: Design Automation Methods for Highly-Complex Multimedia Systems
Time: 10:10 - 12:15 Wednesday, January 22, 2014
Location: Room 302
Organizer: Sri Parameswaran (Univ. of New South Wales, Australia)

4S-1 (Time: 10:10 - 10:40)

Title	(Invited Paper) SDG2KPN: System Dependency Graph to Function-Level KPN Generation of Legacy Code for MPSoCs
Author	Jude Angelo Ambrose, Jorgen Peddersen (Univ. of New South Wales, Australia), Alvin Labios, Yusuke Yachide (Canon Information Systems Research Australia (CiSRA), Australia), *Sri Parameswaran (Univ. of New South Wales, Australia)
Page	pp. 267 - 273
Detailed information (abstract, keywords, etc)
Slides

4S-2 (Time: 10:40 - 11:10)

Title	(Invited Paper) Low Power Design of the Next-Generation High Efficiency Video Coding
Author	*Muhammad Shafique, Jörg Henkel (Karlsruhe Inst. of Tech., Germany)
Page	pp. 274 - 281
Detailed information (abstract, keywords, etc)
Slides

4S-3 (Time: 11:10 - 11:40)

Title	(Invited Paper) Mapping Complex Algorithm into FPGA with High Level Synthesis
Author	*Kazutoshi Wakabayashi, Takashi Takenaka, Hiroaki Inoue (NEC, Japan)
Page	pp. 282 - 284
Detailed information (abstract, keywords, etc)

4S-4 (Time: 11:40 - 12:10)

Title	(Invited Paper) Leveraging Parallelism in the Presence of Control Flow on CGRAs
Author	Jihyun Ryoo, Kyuseung Han, *Kiyoung Choi (Seoul National Univ., Republic of Korea)
Page	pp. 285 - 291
Detailed information (abstract, keywords, etc)
Slides

Session 4A System-Level Thermal and Power Optimization Techniques
Time: 10:10 - 12:15 Wednesday, January 22, 2014
Location: Room 300
Chairs: Yun (Eric) Liang (Peking Univ., China), Wengfai Wong (National Univ. of Singapore, Singapore)

4A-1 (Time: 10:10 - 10:35)

Title	Physical-Aware Task Migration Algorithm for Dynamic Thermal Management of SMT Multi-Core Processors
Author	Bagher Salami (Ferdowsi Univ. of Mashhad, Iran), Mohammadreza Baharani (Univ. of Tehran, Iran), Hamid Noori (Ferdowsi Univ. of Mashhad, Iran), *Farhad Mehdipour (Kyushu Univ., Japan)
Page	pp. 292 - 297
Detailed information (abstract, keywords, etc)
Slides

4A-2 (Time: 10:35 - 11:00)

Title	Agile Frequency Scaling for Adaptive Power Allocation in Many-Core Systems Powered by Renewable Energy Sources
Author	*Xiaohang Wang, Zhiming Li (Guangzhou Institute of Advanced Technology, CAS, China), Mei Yang, Yingtao Jiang (Univ. of Nevada, Las Vegas, U.S.A.), Masoud Daneshtalab (Univ. of Turku, Finland), Terrence Mak (Chinese Univ. of Hong Kong, China)
Page	pp. 298 - 303
Detailed information (abstract, keywords, etc)
Slides

4A-3 (Time: 11:00 - 11:25)

Title	Variation Aware Voltage Island Formation for Power Efficient Near-Threshold Manycore Architectures
Author	*Ioannis Stamelakos, Sotirios Xydis, Gianluca Palermo, Cristina Silvano (Politecnico di Milano, Italy)
Page	pp. 304 - 310
Detailed information (abstract, keywords, etc)
Slides

4A-4 (Time: 11:25 - 11:50)

Title	An Evaluation of an Energy Efficient Many-Core SoC with Parallelized Face Detection
Author	*Hiroyuki Usui, Jun Tanabe, Toru Sano, Hui Xu, Takashi Miyamori (Toshiba, Japan)
Page	pp. 311 - 316
Detailed information (abstract, keywords, etc)
Slides

4A-5 (Time: 11:50 - 12:15)

Title	Energy Aware Real-Time Scheduling Policy with Guaranteed Security Protection
Author	*Wei Jiang (Univ. of Electronic Science and Tech. of China, China), Ke Jiang (Linköping Univ., Sweden), Xia Zhang (Univ. of Electronic Science and Tech. of China, China), Yue Ma (Univ. of Notre Dame, U.S.A.)
Page	pp. 317 - 322
Detailed information (abstract, keywords, etc)
Slides

Session 4B Emerging Techniques for Future NoC
Time: 10:10 - 12:15 Wednesday, January 22, 2014
Location: Room 301
Chairs: Paul Bogdan (Univ. of Southern California, U.S.A.), Wei Zhang (HKUST, Hong Kong)

4B-1 (Time: 10:10 - 10:35)

Title	A Comprehensive and Accurate Latency Model for Network-on-Chip Performance Analysis
Author	*Zhiliang Qian (Hong Kong Univ. of Science and Tech., Hong Kong), Da-cheng Juan (Carnegie Mellon Univ., U.S.A.), Paul Bogdan (Univ. of Southern California, U.S.A.), Chi-Ying Tsui (Hong Kong Univ. of Science and Tech., Hong Kong), Diana Marculescu, Radu Marculescu (Carnegie Mellon Univ., U.S.A.)
Page	pp. 323 - 328
Detailed information (abstract, keywords, etc)
Slides

4B-2 (Time: 10:35 - 11:00)

Title	A Low-Latency Asynchronous Interconnection Network with Early Arbitration Resolution
Author	Georgios Faldamis (Cavium, U.S.A.), *Weiwei Jiang (Columbia Univ., U.S.A.), Gennette Gill (D.E. Shaw Research, U.S.A.), Steven M. Nowick (Columbia Univ., U.S.A.)
Page	pp. 329 - 336
Detailed information (abstract, keywords, etc)
Slides

4B-3 (Time: 11:00 - 11:25)

Title	A Vertically Integrated and Interoperable Multi-Vendor Synthesis Flow for Predictable NoC Design in Nanoscale Technologies
Author	*Alberto Ghiribaldi, Herve Tatenguem Fankem (Univ. of Ferrara, Italy), Federico Angiolini (iNoCs, Switzerland), Mikkel Stensgaard, Tobias Bjerregaard (Teklatech, Denmark), Davide Bertozzi (Univ. of Ferrara, Italy)
Page	pp. 337 - 342
Detailed information (abstract, keywords, etc)
Slides

4B-4 (Time: 11:25 - 11:50)

Title	Fuzzy Flow Regulation for Network-on-Chip Based Chip Multiprocessors Systems
Author	*Yuan Yao, Zhonghai Lu (Royal Inst. of Tech., Sweden)
Page	pp. 343 - 348
Detailed information (abstract, keywords, etc)
Slides

4B-5 (Time: 11:50 - 12:15)

Title	Adjustable Contiguity of Run-Time Task Allocation in Networked Many-Core Systems
Author	*Mohammad Fattah, Pasi Liljeberg, Juha Plosila, Hannu Tenhunen (Univ. of Turku, Finland)
Page	pp. 349 - 354
Detailed information (abstract, keywords, etc)
Slides

Session 4C Emerging Applications
Time: 10:10 - 12:15 Wednesday, January 22, 2014
Location: Room 303
Chairs: Yu Wang (Tsinghua Univ., China), Dajiang Zhou (Waseda Univ., Japan)

4C-1 (Time: 10:10 - 10:35)

Title	STD-TLB: A STT-RAM-Based Dynamically-Configurable Translation Lookaside Buffer for GPU Architectures
Author	Xiaoxiao Liu, Yong Li, Yaojun Zhang, Alex K. Jones, *Yiran Chen (Univ. of Pittsburgh, U.S.A.)
Page	pp. 355 - 360
Detailed information (abstract, keywords, etc)
Slides

4C-2 (Time: 10:35 - 11:00)

Title	Training Itself: Mixed-Signal Training Acceleration for Memristor-Based Neural Network
Author	*Boxun Li, Yuzhi Wang, Yu Wang (Tsinghua Univ., China), Yiran Chen (Univ. of Pittsburgh, U.S.A.), Huazhong Yang (Tsinghua Univ., China)
Page	pp. 361 - 366
Detailed information (abstract, keywords, etc)
Slides

4C-3 (Time: 11:00 - 11:25)

Title	HDTV1080p HEVC Intra Encoder with Source Texture Based CU/PU Mode Pre-decision
Author	*Jia Zhu, Zhenyu Liu, Dongsheng Wang (Tsinghua Univ., China), Qingrui Han, Yang Song (Huawei Technologies, China)
Page	pp. 367 - 372
Detailed information (abstract, keywords, etc)
Slides

4C-4 (Time: 11:25 - 11:50)

Title	Fast Large-Scale Optimal Power Flow Analysis for Smart Grid through Network Reduction
Author	*Yi Liang, Deming Chen (Univ. of Illinois, Urbana-Champaign, U.S.A.)
Page	pp. 373 - 378
Detailed information (abstract, keywords, etc)

4C-5 (Time: 11:50 - 12:15)

Title	Storage-Less and Converter-Less Maximum Power Point Tracking of Photovoltaic Cells for a Nonvolatile Microprocessor
Author	*Cong Wang (Tsinghua Univ., China), Naehyuck Chang, Younghyun Kim, Sangyoung Park (Seoul National Univ., Republic of Korea), Yongpan Liu (Tsinghua Univ., China), Hyung Gyu Lee (Daegu Univ., Republic of Korea), Rong Luo, Huazhong Yang (Tsinghua Univ., China)
Page	pp. 379 - 384
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Slides

Session 5S Special Session: Billion Chips of Trillion Transistors
Time: 13:50 - 15:30 Wednesday, January 22, 2014
Location: Room 302
Organizer: Chen-Yong Cher (IBM, U.S.A.)

5S-1 (Time: 13:50 - 14:20)

Title	(Invited Paper) Soft Error Resiliency Characterization on IBM BlueGene/Q Processor
Author	*Chen-Yong Cher, K. Paul Muller, Ruud A. Haring, David L. Satterfield, Thomas E. Musta, Thomas M. Gooding, Kristan D. Davis, Marc B. Dombrowa, Gerard V. Kopcsay, Robert M. Senger, Yutaka Sugawara, Krishnan Sugavanam (IBM, U.S.A.)
Page	pp. 385 - 387
Detailed information (abstract, keywords, etc)

5S-2 (Time: 14:20 - 14:50)

Title	(Invited Paper) Resiliency for Many-Core System on a Chip
Author	*Tanay Karnik, James Tschanz, Nitin Borkar, Jason Howard, Sriram Vangal, Vivek De, Shekhar Borkar (Intel, U.S.A.)
Page	pp. 388 - 389
Detailed information (abstract, keywords, etc)

5S-3 (Time: 14:50 - 15:20)

Title	(Invited Paper) Rethinking Error Injection for Effective Resilience
Author	Shahrzad Mirkhani (Univ. of Texas, U.S.A.), Hyungmin Cho, Subhasish Mitra (Stanford Univ., U.S.A.), *Jacob Abraham (Univ. of Texas, U.S.A.)
Page	pp. 390 - 393
Detailed information (abstract, keywords, etc)
Slides

Session 5A Simulation and Modeling
Time: 13:50 - 15:30 Wednesday, January 22, 2014
Location: Room 300
Chairs: Atushi Ike (Fujitsu Labs., Japan), Yuichi Nakamura (NEC, Japan)

5A-1 (Time: 13:50 - 14:15)

Title	Amphisbaena: Modeling Two Orthogonal Ways to Hunt on Heterogeneous Many-Cores
Author	*Jun Ma, Guihai Yan, Yinhe Han, Xiaowei Li (Chinese Academy of Sciences, China)
Page	pp. 394 - 399
Detailed information (abstract, keywords, etc)

5A-2 (Time: 14:15 - 14:40)

Title	Co-Simulation Framework for Streamlining Microprocessor Development on Standard ASIC Design Flow
Author	*Tomoyuki Nakabayashi, Tomoyuki Sugiyama, Takahiro Sasaki (Mie Univ., Japan), Eric Rotenberg (North Carolina State Univ., U.S.A.), Toshio Kondo (Mie Univ., Japan)
Page	pp. 400 - 405
Detailed information (abstract, keywords, etc)
Slides

5A-3 (Time: 14:40 - 15:05)

Title	Annotation and Analysis Combined Cache Modeling for Native Simulation
Author	Rongjie Yan (Chinese Academy of Sciences, China), *De Ma (Hangzhou Dianzi Univ., China), Kai Huang, Xiaoxu Zhang, Siwen Xiu (Zhejiang Univ., China)
Page	pp. 406 - 411
Detailed information (abstract, keywords, etc)

5A-4 (Time: 15:05 - 15:30)

Title	A Scorchingly Fast FPGA-Based Precise L1 LRU Cache Simulator
Author	*Josef Schneider, Jorgen Peddersen, Sri Parameswaran (Univ. of New South Wales, Australia)
Page	pp. 412 - 417
Detailed information (abstract, keywords, etc)
Slides

Session 5B Reliability Analysis and Enhencement
Time: 13:50 - 15:30 Wednesday, January 22, 2014
Location: Room 301
Chair: Shigeki Nojima (Toshiba, Japan)

5B-1 (Time: 13:50 - 14:15)

Title	Redundant-Via-Aware ECO Routing
Author	*Hsi-An Chien, Ting-Chi Wang (National Tsing Hua Univ., Taiwan)
Page	pp. 418 - 423
Detailed information (abstract, keywords, etc)

5B-2 (Time: 14:15 - 14:40)

Title	A Fast and Provably Bounded Failure Analysis of Memory Circuits in High Dimensions
Author	Wei Wu, Fang Gong (Univ. of California, Los Angeles, U.S.A.), Gengsheng Chen (Fudan Univ., China), *Lei He (Univ. of California, Los Angeles, U.S.A.)
Page	pp. 424 - 429
Detailed information (abstract, keywords, etc)
Slides

5B-3 (Time: 14:40 - 15:05)

Title	Predicting Circuit Aging Using Ring Oscillators
Author	Deepashree Sengupta, *Sachin Sapatnekar (Univ. of Minnesota, U.S.A.)
Page	pp. 430 - 435
Detailed information (abstract, keywords, etc)
Slides

5B-4 (Time: 15:05 - 15:30)

Title	Statistical Analysis of Process Variation Based on Indirect Measurements for Electronic System Design
Author	*Ivan Ukhov, Mattias Villani, Petru Eles, Zebo Peng (Linköping Univ., Sweden)
Page	pp. 436 - 442
Detailed information (abstract, keywords, etc)
Slides

Session 5C Variational Design Techniques for Analog/Mixed-Signal Circuits
Time: 13:50 - 15:30 Wednesday, January 22, 2014
Location: Room 303
Chairs: C.Y. Tsui (Hong Kong Univ. of Science and Tech., Hong Kong), Hideki Asai (Shizuoka Univ., Japan)

5C-1 (Time: 13:50 - 14:15)

Title	Symbolic Computation of SNR for Variational Analysis of Sigma-Delta Modulator
Author	*Jiandong Cheng, Guoyong Shi (Shanghai Jiao Tong Univ., China)
Page	pp. 443 - 448
Detailed information (abstract, keywords, etc)

5C-2 (Time: 14:15 - 14:40)

Title	Sparse Statistical Model Inference for Analog Circuits under Process Variations
Author	*Yan Zhang, Sriram Sankaranarayanan, Fabio Somenzi (Univ. of Colorado, Boulder, U.S.A.)
Page	pp. 449 - 454
Detailed information (abstract, keywords, etc)
Slides

5C-3 (Time: 14:40 - 15:05)

Title	Time-Domain Performance Bound Analysis for Analog and Interconnect Circuits Considering Process Variations
Author	*Tan Yu, Sheldon Tan (Univ. of California, Riverside, U.S.A.), Yici Cai (Tsinghua Univ., China), Puying Tang (Univ. of Electronic Science and Tech. of China, China)
Page	pp. 455 - 460
Detailed information (abstract, keywords, etc)
Slides

5C-4 (Time: 15:05 - 15:30)

Title	A Robustness Optimization of SRAM Dynamic Stability by Sensitivity-Based Reachability Analysis
Author	Yang Song, *Sai Manoj P. D., Hao Yu (Nanyang Technological Univ., Singapore)
Page	pp. 461 - 466
Detailed information (abstract, keywords, etc)
Slides

Session 6S Special Session: Overcoming Major Silicon Bottlenecks: Variability, Reliability, Validation and Debug
Time: 15:50 - 17:30 Wednesday, January 22, 2014
Location: Room 302
Organizer: Subhasish Mitra (Stanford Univ., U.S.A.)

6S-1 (Time: 15:50 - 16:20)

Title	(Invited Paper) Accurate and Inexpensive Performance Monitoring for Variability-Aware Systems
Author	Liangzhen Lai, *Puneet Gupta (UCLA, U.S.A.)
Page	pp. 467 - 473
Detailed information (abstract, keywords, etc)

6S-2 (Time: 16:20 - 16:50)

Title	(Invited Paper) Quantifying Workload Dependent Reliability in Embedded Processors
Author	*Vikas Chandra (ARM, U.S.A.)
Page	pp. 474 - 477
Detailed information (abstract, keywords, etc)

6S-3 (Time: 16:50 - 17:20)

Title	(Invited Paper) QED Post-Silicon Validation and Debug: Frequently Asked Questions
Author	David Lin, *Subhasish Mitra (Stanford Univ., U.S.A.)
Page	pp. 478 - 482
Detailed information (abstract, keywords, etc)

Session 6A Synthesis of Quantum Circuits and Adaptive Logic
Time: 15:50 - 17:30 Wednesday, January 22, 2014
Location: Room 300
Chairs: Yusuke Matsunaga (Kyushu Univ., Japan), Deming Chen (Univ. of Illinois, Urbana-Champaign, U.S.A.)

6A-1 (Time: 15:50 - 16:15)

Title	Efficient Synthesis of Quantum Circuits Implementing Clifford Group Operations
Author	*Philipp Niemann (Univ. of Bremen, Germany), Robert Wille (Univ. of Bremen/Cyber Physical Systems DFKI GmbH/Technical Univ. Dresden, Germany), Rolf Drechsler (Univ. of Bremen/Cyber Physical Systems DFKI GmbH, Germany)
Page	pp. 483 - 488
Detailed information (abstract, keywords, etc)
Slides

6A-2 (Time: 16:15 - 16:40)

Title	Optimal SWAP Gate Insertion for Nearest Neighbor Quantum Circuits
Author	*Robert Wille (Univ. of Bremen/Cyber Physical Systems DFKI GmbH/Technical Univ. Dresden, Germany), Aaron Lye (Univ. of Bremen, Germany), Rolf Drechsler (Univ. of Bremen/Cyber Physical Systems DFKI GmbH, Germany)
Page	pp. 489 - 494
Detailed information (abstract, keywords, etc)
Slides

6A-3 (Time: 16:40 - 17:05)

Title	Qubit Placement to Minimize Communication Overhead in 2D Quantum Architectures
Author	Alireza Shafaei, Mehdi Saeedi, *Massoud Pedram (Univ. of Southern California, U.S.A.)
Page	pp. 495 - 500
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Slides

6A-4 (Time: 17:05 - 17:30)

Title	A Novel Wirelength-Driven Packing Algorithm for FPGAs with Adaptive Logic Modules
Author	Sheng-Kai Wu, *Po-Yi Hsu, Wai-Kei Mak (National Tsing Hua Univ., Taiwan)
Page	pp. 501 - 506
Detailed information (abstract, keywords, etc)
Slides

Session 6B Contemporary Routing
Time: 15:50 - 17:30 Wednesday, January 22, 2014
Location: Room 301
Chairs: Mark Lin (National Chung Cheng Univ., Taiwan), Toshiyuki Shibuya (Fujitsu Labs., Japan)

6B-1 (Time: 15:50 - 16:15)

Title	A Topology-Based ECO Routing Methodology for Mask Cost Minimization
Author	*Po-Hsun Wu, Shang-Ya Bai, Tsung-Yi Ho (National Cheng Kung Univ., Taiwan)
Page	pp. 507 - 512
Detailed information (abstract, keywords, etc)

6B-2 (Time: 16:15 - 16:40)

Title	BOB-Router: A New Buffering-Aware Global Router with Over-the-Block Routing Resources Optimization
Author	Yilin Zhang (Univ. of Texas, Austin, U.S.A.), Salim Chowdhury (Oracle, U.S.A.), *David Z. Pan (Univ. of Texas, Austin, U.S.A.)
Page	pp. 513 - 518
Detailed information (abstract, keywords, etc)
Slides

6B-3 (Time: 16:40 - 17:05)

Title	Routability-Driven Bump Assignment for Chip-Package Co-Design
Author	Meng-Ling Chen, Tu-Hsiung Tsai, *Hung-Ming Chen (National Chiao Tung Univ., Taiwan), Shi-Hao Chen (Global Unichip, Taiwan)
Page	pp. 519 - 524
Detailed information (abstract, keywords, etc)
Slides

6B-4 (Time: 17:05 - 17:30)

Title	VFGR: A Very Fast Parallel Global Router with Accurate Congestion Modeling
Author	*Zhongdong Qi, Yici Cai, Qiang Zhou (Tsinghua Univ., China), Zhuoyuan Li, Mike Chen (Nimbus Automation Technologies, China)
Page	pp. 525 - 530
Detailed information (abstract, keywords, etc)
Slides

Session 6C Power Supply Noise Aware Design Optimization
Time: 15:50 - 17:30 Wednesday, January 22, 2014
Location: Room 303
Chairs: Wenjian Yu (Tsinghua Univ., China), Shi Guoyong (Shanghai Jiao Tong Univ., China)

6C-1 (Time: 15:50 - 16:15)

Title	Efficient Simulation-Based Optimization of Power Grid with On-Chip Voltage Regulator
Author	Ting Yu, *Martin D.F. Wong (Univ. of Illinois, Urbana-Champaign, U.S.A.)
Page	pp. 531 - 536
Detailed information (abstract, keywords, etc)
Slides

6C-2 (Time: 16:15 - 16:40)

Title	Walking Pads: Fast Power-Supply Pad-Placement Optimization
Author	Ke Wang (Univ. of Virginia, U.S.A.), *Brett Meyer (McGill Univ., Canada), Runjie Zhang, Kevin Skadron, Mircea Stan (Univ. of Virginia, U.S.A.)
Page	pp. 537 - 543
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6C-3 (Time: 16:40 - 17:05)

Title	Power Supply Noise-Aware Workload Assignments for Homogenous 3D MPSoCs with Thermal Consideration
Author	*Yuanqing Cheng (LIRMM, France), Aida Todri-Sanial (CNRS/LIRMM, France), Alberto Bosio (Univ. of Montpellier/LIRMM, France), Luigi Dilillo, Patrick Girard (CNRS/LIRMM, France), Arnaud Virazel (Univ. of Montpellier/LIRMM, France)
Page	pp. 544 - 549
Detailed information (abstract, keywords, etc)
Slides

6C-4 (Time: 17:05 - 17:30)

Title	SwimmingLane: A Composite Approach to Mitigate Voltage Droop Effects in 3D Power Delivery Network
Author	*Xing Hu (Univ. of Chinese Academy of Sciences, China), Yi Xu (Macau Univ. of Science and Tech., Macau/AMD, China), Yu Hu (Univ. of Chinese Academy of Sciences, China), Yuan Xie (AMD, China/Pennsylvania State Univ., U.S.A.)
Page	pp. 550 - 555
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Slides

Session BK Banquet & Banquet Keynote
Time: 18:30 - 21:00 Wednesday, January 22, 2014
Location: Flower Field Hall, Gardens by the Bay
Chair: Mashiro Fujita (Univ. of Tokyo, Japan)

BK-1 (Time: 19:30 - 20:00)

Title	(Keynote Address) The Art of Innovation - How Singapore Will Continue to Drive the Progress in Semiconductor Technologies
Author	Ulf Schneider (Managing Director, Lantiq Asia Pacific/President, SSIA, Singapore)
Detailed information (abstract, keywords, etc)

Thursday, January 23, 2014

Session 3K Keynote III
Time: 8:30 - 9:30 Thursday, January 23, 2014
Location: Room 300
Chair: Naehyuck Chang (Seoul National Univ., Republic of Korea)

3K-1 (Time: 8:30 - 9:30)

Title	(Keynote Address) Beyond Charge-Based Computing
Author	Kaushik Roy (Purdue Univ., U.S.A.)
Detailed information (abstract, keywords, etc)

Session 7S Special Session: Brain Like Computing: Modelling, Technology, and Architecture
Time: 10:10 - 12:15 Thursday, January 23, 2014
Location: Room 302
Chair: Ahmed Hemani (KTH, Sweden)

7S-1 (Time: 10:10 - 10:40)

Title	(Invited Paper) Spiking Brain Models: Computation, Memory and Communication Constraints for Custom Hardware Implementation
Author	*Anders Lansner, Ahmed Hemani, Nasim Farahini (KTH, Sweden)
Page	pp. 556 - 562
Detailed information (abstract, keywords, etc)

7S-2 (Time: 10:40 - 11:10)

Title	(Invited Paper) Advanced Technologies for Brain-Inspired Computing
Author	*Fabien Clermidy, Rodolphe Heliot, Alexandre Valentian (CEA-LETI, France), Christian Gamrat, Olivier Bichler, Marc Duranton (CEA-LIST, France), Bilel Blehadj, Olivier Temam (INRIA, France)
Page	pp. 563 - 569
Detailed information (abstract, keywords, etc)
Slides

7S-3 (Time: 11:10 - 11:40)

Title	(Invited Paper) GPGPU Accelerated Simulation and Parameter Tuning for Neuromorphic Applications
Author	Kristofor D. Carlson, Michael Beyeler, *Nikil Dutt, Jeffrey L. Krichmar (UC Irvine, U.S.A.)
Page	pp. 570 - 577
Detailed information (abstract, keywords, etc)
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7S-4 (Time: 11:40 - 12:10)

Title	(Invited Paper) A Scalable Custom Simulation Machine for the Bayesian Confidence Propagation Neural Network Model of the Brain
Author	Nasim Farahini, *Ahmed Hemani, Anders Lansner (KTH, Sweden), Fabian Clermidy (CEA-LETI, France), Christer Svensson (Linköping Univ., Sweden)
Page	pp. 578 - 585
Detailed information (abstract, keywords, etc)

Session 7A Power and Life Time Issues of Memory Subsystem
Time: 10:10 - 12:15 Thursday, January 23, 2014
Location: Room 300
Chairs: Muhammad Shafique (Karlsruhe Inst. of Tech., Germany), Wei Zhang (Hong Kong Univ. of Science and Tech., Hong Kong)

7A-1 (Time: 10:10 - 10:35)

Title	No△:Leveraging Delta Compression for End-to-End Memory Access in NoC Based Multicores
Author	*Jia Zhan, Matt Poremba (Pennsylvania State Univ., U.S.A.), Yi Xu (AMD Research, China), Yuan Xie (AMD, China/Pennsylvania State Univ., U.S.A.)
Page	pp. 586 - 591
Detailed information (abstract, keywords, etc)
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7A-2 (Time: 10:35 - 11:00)

Title	DPA: A Data Pattern Aware Error Prevention Technique for NAND Flash Lifetime Extension
Author	Jie Guo, Zhijie Chen (Univ. of Pittsburgh, U.S.A.), Danghui Wang (Northwestern Polytechnical Univ., China), Zili Shao (Hong Kong Polytechnic Univ., Hong Kong), *Yiran Chen (Univ. of Pittsburgh, U.S.A.)
Page	pp. 592 - 597
Detailed information (abstract, keywords, etc)
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7A-3 (Time: 11:00 - 11:25)

Title	Scattered Refresh: An Alternative Refresh Mechanism to Reduce Refresh Cycle Time
Author	*T. Venkata Kalyan, Ravi Kasha, Madhu Mutyam (Indian Inst. of Tech. - Madras, India)
Page	pp. 598 - 603
Detailed information (abstract, keywords, etc)
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7A-4 (Time: 11:25 - 11:50)

Title	A Read-Write Aware DRAM Scheduling for Power Reduction in Multi-Core Systems
Author	*Chih-Yen Lai, Gung-Yu Pan, Hsien-Kai Kuo (National Chiao Tung Univ., Taiwan), Jing-Yang Jou (National Central Univ./National Chiao Tung Univ., Taiwan)
Page	pp. 604 - 609
Detailed information (abstract, keywords, etc)
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7A-5 (Time: 11:50 - 12:15)

Title	A Coherent Hybrid SRAM and STT-RAM L1 Cache Architecture for Shared Memory Multicores
Author	*Jianxing Wang, Yenni Tim, Weng-Fai Wong, Zhong-Liang Ong (National Univ. of Singapore, Singapore), Zhenyu Sun, Hai (Helen) Li (Univ. of Pittsburgh, U.S.A.)
Page	pp. 610 - 615
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Session 7B Advances in High-Level and Logic Synthesis
Time: 10:10 - 12:15 Thursday, January 23, 2014
Location: Room 301
Chairs: Yuko Hara-Azumi (NAIST, Japan), Robert Wille (Univ. of Bremen, Germany)

7B-1 (Time: 10:10 - 10:35)

Title	Allocation of FPGA DSP-Macros in Multi-Process High-Level Synthesis Systems
Author	*Benjamin Carrion Schafer (Hong Kong Polytechnic Univ., Hong Kong)
Page	pp. 616 - 621
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7B-2 (Time: 10:35 - 11:00)

Title	Array Scalarization in High Level Synthesis
Author	Preeti Ranjan Panda, *Namita Sharma (Indian Inst. of Tech. Delhi, India), Arun Kumar Pilania, Gummidipudi Krishnaiah, Sreenivas Subramoney, Ashok Jagannathan (Intel Technology India Pvt., India)
Page	pp. 622 - 627
Detailed information (abstract, keywords, etc)
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7B-3 (Time: 11:00 - 11:25)

Title	Data Compression via Logic Synthesis
Author	*Luca Amaru, Pierre-Emmanuel Gaillardon (EPFL-LSI, Switzerland), Andreas Burg (EPFL-TCL, Switzerland), Giovanni De Micheli (EPFL-LSI, Switzerland)
Page	pp. 628 - 633
Detailed information (abstract, keywords, etc)
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7B-4 (Time: 11:25 - 11:50)

Title	Synthesis of Power- and Area-Efficient Binary Machines for Incompletely Specified Sequences
Author	*Nan Li, Elena Dubrova (Royal Inst. of Tech., Sweden)
Page	pp. 634 - 639
Detailed information (abstract, keywords, etc)
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7B-5 (Time: 11:50 - 12:15)

Title	Multi-Mode Trace Signal Selection for Post-Silicon Debug
Author	*Min Li, Azadeh Davoodi (Univ. of Wisconsin - Madison, U.S.A.)
Page	pp. 640 - 645
Detailed information (abstract, keywords, etc)
Slides

Session 7C Advanced Test Solutions
Time: 10:10 - 12:15 Thursday, January 23, 2014
Location: Room 303
Chairs: Jiun-Lang Huang (National Taiwan Univ., Taiwan), Mango Chia-Tso Chao (National Chiao Tung Univ., Taiwan)

7C-1 (Time: 10:10 - 10:35)

Title	Implicit Intermittent Fault Detection in Distributed Systems
Author	*Peter Waszecki, Matthias Kauer, Martin Lukasiewycz (TUM CREATE, Singapore), Samarjit Chakraborty (TU Munich, Germany)
Page	pp. 646 - 651
Detailed information (abstract, keywords, etc)
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7C-2 (Time: 10:35 - 11:00)

Title	A Segmentation-Based BISR Scheme
Author	Georgios Zervakis, Nikolaos Eftaxiopoulos, Kostas Tsoumanis, Nicholas Axelos, *Kiamal Pekmestzi (National Technical Univ. of Athens, Greece)
Page	pp. 652 - 657
Detailed information (abstract, keywords, etc)
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7C-3 (Time: 11:00 - 11:25)

Title	Fault-Tolerant TSV by Using Scan-Chain Test TSV
Author	*Fu-Wei Chen, Hui-Ling Ting, TingTing Hwang (National Tsing Hua Univ., Taiwan)
Page	pp. 658 - 663
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7C-4 (Time: 11:25 - 11:50)

Title	Suppressing Test Inflation in Shared-Memory Parallel Automatic Test Pattern Generation
Author	Jerry C. Y. Ku, Ryan H.-M. Huang, Louis Y. -Z. Lin, *Charles H.-P. Wen (National Chiao Tung Univ., Taiwan)
Page	pp. 664 - 669
Detailed information (abstract, keywords, etc)

7C-5 (Time: 11:50 - 12:15)

Title	A Volume Diagnosis Method for Identifying Systematic Faults in Lower-Yield Wafer Occurring during Mass Production
Author	*Tsutomu Ishida, Izumi Nitta (Fujitsu Labs., Japan), Koji Banno (Fujitsu Semiconductor, Japan), Yuzi Kanazawa (Fujitsu Labs., Japan)
Page	pp. 670 - 675
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Session 8S Special Session: Design Flow for Integrated Circuits using Magnetic Tunnel Junction Switched by Spin Orbit Torque
Time: 13:50 - 15:30 Thursday, January 23, 2014
Location: Room 302
Organizer: Mehdi Tahoori (Karlsruhe Inst. of Tech., Germany)

8S-1 (Time: 13:50 - 14:15)

Title	(Invited Paper) An Overview of Spin-Based Integrated Circuits
Author	Wang Kang (Univ. Beihang, China/Univ. Paris-Sud, France), *Weisheng Zhao, Zhaohao Wang, Jacques-Olivier Klein, Yue Zhang, Djaafar Chabi (Univ. Paris-Sud, France), Youguang Zhang (Univ. Beihang, China), Dafiné Ravelosona, Claude Chappert (Univ. Paris-Sud, France)
Page	pp. 676 - 683
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8S-2 (Time: 14:15 - 14:40)

Title	(Invited Paper) Advances in Spintronics Devices for Microelectronics - from Spin-Transfer Torque to Spin-Orbit Torque
Author	*Shunsuke Fukami, Hideo Sato, Michihiko Yamanouchi, Shoji Ikeda, Fumihiro Matsukura, Hideo Ohno (Tohoku Univ., Japan)
Page	pp. 684 - 691
Detailed information (abstract, keywords, etc)

8S-3 (Time: 14:40 - 15:05)

Title	(Invited Paper) Hybrid CMOS/Magnetic Process Design Kit and SOT-Based Non-Volatile Standard Cell Architectures
Author	*Gregory Di Pendina, Kotb Jabeur, Guillaume Prenat (Spintec Laboratory, CEA-INAC/CNRS/UJF/G-INP, France)
Page	pp. 692 - 699
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8S-4 (Time: 15:05 - 15:30)

Title	(Invited Paper) Architectural Aspects in Design and Analysis of SOT-Based Memories
Author	Rajendra Bishnoi, Mojtaba Ebrahimi, Fabian Oboril, *Mehdi Tahoori (Karlsruhe Inst. of Tech., Germany)
Page	pp. 700 - 707
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Session 8A Analysis, Optimization, and Scheduling for Multiprocessor Platforms
Time: 13:50 - 15:30 Thursday, January 23, 2014
Location: Room 300
Chairs: Sebastian Steinhorst (TUM CREATE, Singapore), Akash Kumar (National Univ. of Singapore, Singapore)

8A-1 (Time: 13:50 - 14:15)

Title	Timing Anomalies in Multi-Core Architectures due to the Interference on the Shared Resources
Author	*Hardik Shah, Kai Huang, Alois Knoll (Technical Univ. Munich, Germany)
Page	pp. 708 - 713
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8A-2 (Time: 14:15 - 14:40)

Title	A Unified Online Directed Acyclic Graph Flow Manager for Multicore Schedulers
Author	*Karim Kanoun, David Atienza (École Polytechnique Fédérale de Lausanne, Switzerland), Nicholas Mastronarde (State Univ. of New York at Buffalo, U.S.A.), Mihaela van der Schaar (Univ. of California, Los Angeles, U.S.A.)
Page	pp. 714 - 719
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8A-3 (Time: 14:40 - 15:05)

Title	Variation-Aware Statistical Energy Optimization on Voltage-Frequency Island Based MPSoCs under Performance Yield Constraints
Author	*Song Jin (North China Electric Power Univ., China), Yinhe Han (Chinese Academy of Sciences, China), Songwei Pei (Beijing Univ. of Chemical Tech., China)
Page	pp. 720 - 725
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8A-4 (Time: 15:05 - 15:30)

Title	QoS-Aware Dynamic Resource Allocation for Spatial-Multitasking GPUs
Author	*Paula Aguilera, Katherine Morrow, Nam Sung Kim (Univ. of Wisconsin - Madison, U.S.A.)
Page	pp. 726 - 731
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Session 8B Advances in Formal Verification and Debugging
Time: 13:50 - 15:30 Thursday, January 23, 2014
Location: Room 301
Chairs: Charles H.-P. Wen (National Chiao Tung Univ., Taiwan), Vishvender Singh (Infineon Technologies Asia-Pacific, Singapore)

8B-1 (Time: 13:50 - 14:15)

Title	Automated Debugging of Missing Assumptions
Author	Brian Keng (Univ. of Toronto, Canada), Evean Qin (Vennsa Technologies, Canada), *Andreas Veneris, Bao Le (Univ. of Toronto, Canada)
Page	pp. 732 - 737
Detailed information (abstract, keywords, etc)
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8B-2 (Time: 14:15 - 14:40)

Title	Property Directed Reachability for QF_BV with Mixed Type Atomic Reasoning Units
Author	*Tobias Welp (Univ. of California, Berkeley, U.S.A.), Andreas Kuehlmann (Coverity/Univ. of California, Berkeley, U.S.A.)
Page	pp. 738 - 743
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8B-3 (Time: 14:40 - 15:05)

Title	Adaptive Interpolation-Based Model Checking
Author	*Chien-Yu Lai, Cheng-Yin Wu, Chung-Yan (Ric) Huang (National Taiwan Univ., Taiwan)
Page	pp. 744 - 749
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8B-4 (Time: 15:05 - 15:30)

Title	Efficient Parallel GPU Algorithms for BDD Manipulation
Author	*Miroslav Velev, Ping Gao (Aries Design Automation, U.S.A.)
Page	pp. 750 - 755
Detailed information (abstract, keywords, etc)

Session 8C Advances in CAD Techniques for Signal Integrity
Time: 13:50 - 15:30 Thursday, January 23, 2014
Location: Room 303
Chairs: Rung-Bin Lin (Yuan Ze Univ., Taiwan), Sheldon Tan (Univ. of California, Riverside, U.S.A.)

8C-1 (Time: 13:50 - 14:15)

Title	Efficient Techniques for the Capacitance Extraction of Chip-Scale VLSI Interconnects Using Floating Random Walk Algorithm
Author	*Chao Zhang, Wenjian Yu (Tsinghua Univ., China)
Page	pp. 756 - 761
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8C-2 (Time: 14:15 - 14:40)

Title	3DLAT: TSV-Based 3D ICs Crosstalk Minimization Utilizing Less Adjacent Transition Code
Author	*Qiaosha Zou, Dimin Niu, Yan Cao (Pennsylvania State Univ., U.S.A.), Yuan Xie (AMD, China/Pennsylvania State Univ., U.S.A.)
Page	pp. 762 - 767
Detailed information (abstract, keywords, etc)
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8C-3 (Time: 14:40 - 15:05)

Title	Tackling Close-to-Band Passivity Violations in Passive Macro-Modeling
Author	*Moning Zhang, Zuochang Ye (Tsinghua Univ., China)
Page	pp. 768 - 773
Detailed information (abstract, keywords, etc)
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8C-4 (Time: 15:05 - 15:30)

Title	HIE-Block Latency Insertion Method for Fast Transient Simulation of Nonuniform Multiconductor Transmission Lines
Author	*Takahiro Takasaki, Tadatoshi Sekine, Hideki Asai (Shizuoka Univ., Japan)
Page	pp. 774 - 779
Detailed information (abstract, keywords, etc)
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Session 9S Special Session: The Role of Photons in Harming or Increasing Security
Time: 15:50 - 17:30 Thursday, January 23, 2014
Location: Room 302
Organizer: Francesco Regazzoni (Univ. of Lugano, Switzerland), Edoardo Charbon (Delft Univ. of Tech., Netherlands)

9S-1 (Time: 15:50 - 16:30)

Title	(Invited Paper) The Role of Photons in Cryptanalysis
Author	*Juliane Krämer (Univ. Berlin, Germany), Michael Kasper (Fraunhofer Institute for Secure Information Technology, Germany), Jean-Pierre Seifert (Univ. Berlin)
Page	pp. 780 - 787
Detailed information (abstract, keywords, etc)

9S-2 (Time: 16:30 - 17:10)

Title	(Invited Paper) SPADs for Quantum Random Number Generators and Beyond
Author	Samuel Burri (EPFL, Switzerland), Damien Stucki (ID Quantique, Switzerland), Yuki Maruyama (Delft Univ. of Tech., Netherlands), Claudio Bruschini (EPFL, Switzerland), Edoardo Charbon (Delft Univ. of Tech., Netherlands), *Francesco Regazzoni (ALaRI - USI, Switzerland)
Page	pp. 788 - 794
Detailed information (abstract, keywords, etc)

9S-3 (Time: 17:10 - 17:50)

Title	(Invited Paper) Quantum Key Distribution with Integrated Optics
Author	*Mirko Lobino (Griffith Univ., Australia), Anthony Laing (Univ. of Bristol, U.K.), Pei Zhang (Xi'an Jiaotong Univ., U.K.), Kanin Aungskunsiri, Enrique Martin-Lopez (Univ. of Bristol, U.K.), Joachim Wabnig (Nokia Research Centre, U.K.), Richard W. Nock, Jack Munns, Damien Bonneau, Pisu Jiang (Univ. of Bristol, U.K.), Hong Wei Li (Nokia Research Centre, U.K.), John G. Rarity (Univ. of Bristol, U.K.), Antti O. Niskanen (Nokia Research Centre, U.K.), Mark G. Thompson, Jeremy L. O'Brien (Univ. of Bristol, U.K.)
Page	pp. 795 - 799
Detailed information (abstract, keywords, etc)

Session 9A System-Level Verification
Time: 15:50 - 17:30 Thursday, January 23, 2014
Location: Room 300
Chairs: Yinhe Han (Chinese Academy of Sciences, China), Akash Kumar (National Univ. of Singapore, Singapore)

9A-1 (Time: 15:50 - 16:15)

Title	Constraint-Based Platform Variants Specification for Early System Verification
Author	*Andreas Burger, Alexander Viehl, Andreas Braun (FZI Research Center for Information Technology, Germany), Finn Haedicke (solvertec/Univ. of Bremen, Germany), Daniel Große (solvertec, Germany), Oliver Bringmann, Wolfgang Rosenstiel (FZI Research Center for Information Technology/Univ. of Tübingen, Germany)
Page	pp. 800 - 805
Detailed information (abstract, keywords, etc)
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9A-2 (Time: 16:15 - 16:40)

Title	A Transaction-Oriented UVM-Based Library for Verification of Analog Behavior
Author	*Alexander Wolfgang Rath, Volkan Esen, Wolfgang Ecker (Infineon Technologies AG, Germany)
Page	pp. 806 - 811
Detailed information (abstract, keywords, etc)
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9A-3 (Time: 16:40 - 17:05)

Title	Automata-Theoretic Modeling of Fixed-Priority Non-Preemptive Scheduling for Formal Timing Verification
Author	*Matthias Kauer, Sebastian Steinhorst (TUM CREATE, Singapore), Reinhard Schneider (TU Munich, Germany), Martin Lukasiewycz (TUM CREATE, Singapore), Samarjit Chakraborty (TU Munich, Germany)
Page	pp. 812 - 817
Detailed information (abstract, keywords, etc)

Session 9B Modeling and Evaluator for Emerging Technologies
Time: 15:50 - 17:30 Thursday, January 23, 2014
Location: Room 301
Chairs: Guangyu Sun (Peking Univ., China), Wei Zhang (Hong Kong Univ. of Science and Tech., Hong Kong)

9B-1 (Time: 15:50 - 16:15)

Title	PROCEED: A Pareto Optimization-Based Circuit-Level Evaluator for Emerging Devices
Author	*Shaodi Wang, Andrew Pan, Chi On Chui, Puneet Gupta (Univ. of California, Los Angeles, U.S.A.)
Page	pp. 818 - 824
Detailed information (abstract, keywords, etc)
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9B-2 (Time: 16:15 - 16:40)

Title	Modeling and Design Analysis of 3D Vertical Resistive Memory - A Low Cost Cross-Point Architecture
Author	*Cong Xu, Dimin Niu (Pennsylvania State Univ., U.S.A.), Shimeng Yu (Arizona State Univ., U.S.A.), Yuan Xie (AMD, China/Pennsylvania State Univ., U.S.A.)
Page	pp. 825 - 830
Detailed information (abstract, keywords, etc)

9B-3 (Time: 16:40 - 17:05)

Title	The Stochastic Modeling of TiO₂ Memristor and Its Usage in Neuromorphic System Design
Author	Miao Hu (Univ. of Pittsburgh, U.S.A.), Yu Wang (Tsinghua Univ., China), Qinru Qiu (Syracuse Univ., U.S.A.), Yiran Chen, *Hai Li (Univ. of Pittsburgh, U.S.A.)
Page	pp. 831 - 836
Detailed information (abstract, keywords, etc)
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9B-4 (Time: 17:05 - 17:30)

Title	Through-Silicon-Via Inductor: Is It Real or Just A Fantasy?
Author	*Umamaheswara Rao Tida (Missouri Univ. of Science and Tech., U.S.A.), Cheng Zhuo (Intel Research, U.S.A.), Yiyu Shi (Missouri Univ. of Science and Tech., U.S.A.)
Page	pp. 837 - 842
Detailed information (abstract, keywords, etc)
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Session 9C Design and Simulation Toward Power and Temperature Awareness
Time: 15:50 - 17:30 Thursday, January 23, 2014
Location: Room 303
Chairs: Yasuhiro Takashima (Univ. of Kitakyushu, Japan), Yukihide Kohira (Univ. of Aizu, Japan)

9C-1 (Time: 15:50 - 16:15)

Title	Design and Control Methodology for Fine Grain Power Gating Based on Energy Characterization and Code Profiling of Microprocessors
Author	*Kimiyoshi Usami, Masaru Kudo, Kensaku Matsunaga, Tsubasa Kosaka, Yoshihiro Tsurui (Shibaura Inst. of Tech., Japan), Weihan Wang, Hideharu Amano (Keio Univ., Japan), Hiroaki Kobayashi, Ryuichi Sakamoto, Mitaro Namiki (Tokyo Univ. of Agri. and Tech., Japan), Masaaki Kondo (Univ. of Electro-Communications, Japan), Hiroshi Nakamura (Univ. of Tokyo, Japan)
Page	pp. 843 - 848
Detailed information (abstract, keywords, etc)
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9C-2 (Time: 16:15 - 16:40)

Title	A Hybrid Random Walk Algorithm for 3-D Thermal Analysis of Integrated Circuits
Author	*Yuan Liang, Wenjian Yu (Tsinghua Univ., China), Haifeng Qian (IBM, U.S.A.)
Page	pp. 849 - 854
Detailed information (abstract, keywords, etc)

9C-3 (Time: 16:40 - 17:05)

Title	LightSim : A Leakage Aware Ultrafast Temperature Simulator
Author	Smruti R. Sarangi, *Gayathri Ananthanarayanan, M. Balakrishnan (IIT Delhi, India)
Page	pp. 855 - 860
Detailed information (abstract, keywords, etc)
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9C-4 (Time: 17:05 - 17:30)

Title	Fast Vectorless Power Grid Verification Using Maximum Voltage Drop Location Estimation
Author	Wei Zhao, Yici Cai, *Jianlei Yang (Tsinghua Univ., China)
Page	pp. 861 - 866
Detailed information (abstract, keywords, etc)
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The 19th Asia and South Pacific Design Automation Conference Technical Program

Session Schedule

List of Papers

The 19th Asia and South Pacific Design Automation Conference
Technical Program