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The 20th Asia and South Pacific Design Automation Conference

Session 1A  NoCS I (Performance and Fault Tolerance)
Time: 10:20 - 12:00 Tuesday, January 20, 2015
Location: Room 102
Chairs: Yoshinori Takeuchi (Osaka Univ., Japan), Takashi Miyamori (Toshiba)

1A-1 (Time: 10:20 - 10:45)
TitleA Novel Approach Using a Minimum Cost Maximum Flow Algorithm for Fault-Tolerant Topology Reconfiguration in NoC Architectures
AuthorLeibo Liu, *Yu Ren, Chenchen Deng (Tsinghua Univ., China), Jie Han (Univ. of Alberta, Canada), Shouyi Yin, Shaojun Wei (Tsinghua Univ., China)
Pagepp. 48 - 53
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1A-2 (Time: 10:45 - 11:10)
TitleAdaptive Remaining Hop Count Flow Control: Consider the Interaction between Packets
Author*Peng Wang, Sheng Ma, Hongyi Lu, Zhiying Wang, Chen Li (National Univ. of Defense Tech., China)
Pagepp. 54 - 60
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1A-3 (Time: 11:10 - 11:35)
TitleA Flexible Hardware Barrier Mechanism for Many-Core Processors
Author*Takeshi Soga (ISIT Kyushu, JST CREST, Japan), Hiroshi Sasaki, Tomoya Hirao (Kyushu Univ., Japan), Masaaki Kondo (Univ. of Tokyo, Japan), Koji Inoue (Kyushu Univ., Japan)
Pagepp. 61 - 68
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1A-4 (Time: 11:35 - 12:00)
TitleA Performance Enhanced Dual-Switch Network-on-Chip Architecture
Author*Lian Zeng, Takahiro Watanabe (Waseda Univ., Japan)
Pagepp. 69 - 74
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