| Title | A Novel Approach Using a Minimum Cost Maximum Flow Algorithm for Fault-Tolerant Topology Reconfiguration in NoC Architectures |
| Author | Leibo Liu, *Yu Ren, Chenchen Deng (Tsinghua University, China), Jie Han (University of Alberta, Canada), Shouyi Yin, Shaojun Wei (Tsinghua University, China) |
| Page | pp. 48 - 53 |
| Keyword | Network-on-chip, fault tolerance, topology reconfiguration |
| Abstract | An approach using a minimum cost maximum flow algorithm is proposed for fault-tolerant topology reconfiguration in a Network-on-Chip system. Topology reconfiguration is converted into a network flow problem by constructing a directed graph with capacity constraints. A cost factor is considered to differentiate between processing elements. This approach maximizes the use of spare cores to repair faulty systems, with minimal impact on area, throughput and delay. It also provides a transparent virtual topology to alleviate the burden for operating systems. |
| Slides |
| Title | Adaptive Remaining Hop Count Flow Control: Consider the Interaction between Packets |
| Author | *Peng Wang, Sheng Ma, Hongyi Lu, Zhiying Wang, Chen Li (National University of Defense Technology, China) |
| Page | pp. 54 - 60 |
| Keyword | Flow Control, Remaining Hop Count, interaction between packets |
| Abstract | The interaction between packets affects performance and global fairness of Network-on-Chip. Preferentially transferring packets with small remaining hop counts (PPSR) can reduce the flying packet amount to improve the performance. Yet, the global fairness is negatively affected. In contrast, preferentially transferring packets with large remaining hop counts (PPLR) can achieve better global fairness with a poorer performance. In this paper, we propose adaptive remaining hop count flow control, which dynamically switches between PPSR and PPLR. In this way, we can achieve higher performance and better global fairness. |
| Slides |
| Title | A Flexible Hardware Barrier Mechanism for Many-Core Processors |
| Author | *Takeshi Soga (ISIT Kyushu, JST CREST, Japan), Hiroshi Sasaki, Tomoya Hirao (Kyushu University, Japan), Masaaki Kondo (The University of Tokyo, Japan), Koji Inoue (Kyushu University, Japan) |
| Page | pp. 61 - 68 |
| Keyword | Hardware Barrier, On-chip, Flexible, Small Area, Low Latency |
| Abstract | This paper proposes a new hardware barrier mechanism which offers the flexibility to select which cores should join the synchronization, allowing for executing multiple multi-threaded applications by dividing a many-core processor into several groups.
Experimental results based on an RTL simulation show that our hardware barrier achieves a 66-fold reduction in latency over typical software based implementations, with a hardware overhead of the processor of only 1.8%. Additionally, we demonstrate that the proposed mechanism is sufficiently flexible to cover a variety of core groups with minimal hardware overhead. |
| Slides |