| Title | A Cross-Layer Framework for Designing and Optimizing Deeply-Scaled FinFET-Based SRAM Cells under Process Variations |
| Author | *Alireza Shafaei, Shuang Chen, Yanzhi Wang, Massoud Pedram (University of Southern California, U.S.A.) |
| Page | pp. 75 - 80 |
| Keyword | Deeply-scaled FinFET devices, SRAM cell design, Near-threshold computing |
| Abstract | A cross-layer framework (spanning device and circuit levels) is presented for designing robust and energy-efficient SRAM cells, made of deeply-scaled FinFET devices. In particular, 7nm FinFET devices are designed and simulated by using Synopsys TCAD tool suite, Sentaurus. Next, 6T and 8T SRAM cells, which are composed of these devices, are designed and optimized. To enhance the cell stability and reduce leakage energy consumption, the dual (i.e., front and back) gate control feature of FinFETs is exploited. This is, however, done without requiring any external signal to drive the back gates of the FinFET devices. Subsequently, the effect of process variations on the aforesaid SRAMs is investigated and steps are presented to protect the cells against these variations. More precisely, the SRAM cells are first designed to minimize the expected energy consumption (per clock cycle) subject to the non-destructive read and successful write requirements under worst-case process corner conditions. These SRAM cells, which are overly pessimistic, are then refined by selectively adjusting some transistor sizes, which in turn reduces the expected energy consumption while ensuring that the parametric yield of the cells remains above some pre-specified threshold. To do this efficiently, an analytical method for estimating the yield of SRAM cells under process variations is also presented and integrated in the refinement procedure. A dual-gate controlled 6T SRAM cell operating at 324mV (in the near-threshold supply regime) is finally presented as a high-yield and energy-efficient memory cell in the 7nm FinFET technology. |
| Slides |
| Title | Controlled Placement of Standard Cell Memory Arrays for High Density and Low Power in 28nm FD-SOI |
| Author | *Adam Teman (EPFL, Switzerland), Davide Rossi (University of Bologna, Italy), Pascal Meinerzhagen (EPFL, Switzerland), Luca Benini (University of Bologna, Italy/ETH, Switzerland), Andreas Burg (EPFL, Switzerland) |
| Page | pp. 81 - 86 |
| Keyword | Standard Cell Memories, Controlled Placement, Place and Route, Low Voltage Memories, Physical Implementation Methodology |
| Abstract | Standard cell memories (SCMs) have recently become a popular alternative to SRAM IPs due to their design flexibility, ease of implementation,
and robust operation at low supply voltages. Exclusively composed of standard cells, these memory macros are implemented as part of the standard digital design flow. However, the synthesis and place and route (P&R) algorithms employed by this flow do not exploit the distinct and regular structure of a memory array, leaving room for optimization.In this paper, we present a controlled placement design methodology for optimizing the physical implementation of SCM macros, leading to a structured, non-congested layout with close to 100% placement utilization and reduced wirelength as compared to unstructured layouts. Three sample SCM macro sizes were implemented according to the proposed methodology in a state-of-the-art 28nm FD-SOI technology, and compared with equivalent macros designed with the non-controlled, standard flow, achieving as much as a 22% reduction in area, a 57% reduction in switching power, and a 42% reduction in leakage power. In addition, these macros provide as much as an 88% reduction in switching power, as compared to equivalently sized, foundry provided SRAM IPs, while enabling robust functionality well below the minimum operating voltage of these IPs. |
| Slides |
| Title | Stress-Aware P/G TSV Planning in 3D-ICs |
| Author | *Shengcheng Wang, Farshad Firouzi, Fabian Oboril, Mehdi B. Tahoori (Karlsruhe Institute of Technology, Germany) |
| Page | pp. 94 - 99 |
| Keyword | 3D-IC, TSV, Stress, IR-drop, Timing analysis |
| Abstract | Power/Ground (P/G) Through-Silicon-Vias (TSVs) in the Power Distribution Network (PDN) of Three-Dimensional-Integrated-Circuit (3D-IC) have a twofold impact on the delays of the surrounding gates. TSV fabrication causes thermal stress around TSVs, which results in significant carrier mobility variations in their vicinity. On the other hand, the insertion of P/G TSVs will change the voltage of each node in the power grid, which also impacts the delays of the connected gates. Thus, it is necessary to consider the combined effect on delay variation during the P/G TSV planning. In this work, we propose a methodology using Mixed-Integer-Bilinear-Programming (MIBLP) to optimize this delay variation by a refined P/G TSV allocation. Taking into account the impact of thermal stress as well as voltage drop on the circuit delay, we optimally plan the P/G TSVs to minimize the circuit delay for different keep-out zones (KOZs) and PDN pitches. |
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