| Title | Quantitative Modeling of Racetrack Memory, A Tradeoff among Area, Performance, and Power |
| Author | *Chao Zhang, Guangyu Sun, Weiqi Zhang (CECA, Peking University, China), Fan Mi, Hai Li (University of Pittsburgh, U.S.A.), Weisheng Zhao (Spintronics Interdisciplinary Center, Beihang University, China) |
| Page | pp. 100 - 105 |
| Keyword | Racetrack Memory, modeling, Macro Unit, Cache |
| Abstract | Recently, an emerging non-volatile memory called Racetrack Memory (RM) becomes promising to satisfy the requirement of increasing on-chip memory capacity. However, the lack of circuit-level modeling has limited RM design exploration. We develop an RM circuit-level model, with careful study of device configurations and circuit layouts. This model introduces Macro Unit (MU) as the building block of RM. Our case study demonstrates significant variance under area, performance, and energy. In addition, cross-layer optimization is critical for RM as on-chip memory. |
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| Title | Technological Exploration of RRAM Crossbar Array for Matrix-Vector Multiplication |
| Author | *Peng Gu, Boxun Li, Tianqi Tang (Tsinghua University, China), Shimeng Yu, Yu Cao (Arizona State University, U.S.A.), Yu Wang, Huazhong Yang (Tsinghua University, China) |
| Page | pp. 106 - 111 |
| Keyword | RRAM, crossbar array, matrix computation |
| Abstract | The matrix-vector multiplication is the key operation for many computationally intensive algorithms. In recent years, the emerging
metal oxide resistive switching random access memory (RRAM) device
and RRAM crossbar array have demonstrated a promising hardware
realization of the analog matrix-vector multiplication with ultra-high
energy efficiency. In this paper, we analyze the impact of nonlinear voltage-current relationship of RRAM devices and the interconnect resistance as well as other crossbar array parameters on the circuit performance and present a design guide. On top of that, we propose a technological exploration flow for device parameter configuration to overcome the impact of nonideal factors and achieve a better trade-off among performance, energy and reliability for each specific application. The simulation results of a support vector machine (SVM) and MNIST pattern recognition dataset shows that the RRAM crossbar array-based SVM is robust to the input signal fluctuation but sensitive to the tunneling gap deviation. A further resistance resolution test presents that a 4-bit RRAM device is able to realize a recognition accuracy of ~90%, indicating the physical feasibility of RRAM crossbar array-based SVM. In addition, the proposed technological exploration flow is able to achieve 10.98% improvement of recognition accuracy on the MNIST dataset and 26.4% energy savings compared with previous work. |
| Title | Modeling Framework for Cross-Point Resistive Memory Design Emphasizing Reliability and Variability Issues |
| Author | Yang Zheng, Cong Xu (Pennsylvania State University, U.S.A.), *Yuan Xie (Pennsylvania State University/University of California, Santa Barbara, U.S.A.) |
| Page | pp. 112 - 117 |
| Keyword | ReRAM, Reliability, Variability, cross-point structure |
| Abstract | In this paper, pseudo-hard error caused by temporal variation is defined for the first time as a unique type of error in ReRAM cross-point array. A comprehensive model is proposed to numerically evaluate all kinds of reliability and variability issues including voltage drop, read/write disturbance, spatial/temporal variations, and hard errors. Detailed analysis and solutions including dual-port write and test-and-flip strategy are proposed to shed light on reliable ReRAM cross-point memory design. |
| Title | A Defect-Aware Approach for Mapping Reconfigurable Single-Electron Transistor Arrays |
| Author | *Ching-Yi Huang, Chian-Wei Liu, Chun-Yao Wang (National Tsing Hua University, Taiwan), Yung-Chih Chen (Yuan Ze University, Taiwan), Suman Datta, Vijaykrishnan Narayanan (The Pennsylvania State University, U.S.A.) |
| Page | pp. 118 - 123 |
| Keyword | Single-Electron Transistor, Reliability, Area Optimization, Defect-aware mapping algorithm |
| Abstract | Single-Electron Transistor (SET) at room temperature has been demonstrated as a promising device for extending Moore's law due to its ultra low power consumption. However, early realizations of SET array lacked variability and reliability due to their fixed architectures and high defect rates of nanowire segments. Therefore, a reconfigurable version of SET was proposed to deal with these issues. Recently, several automated mapping approaches were proposed for area minimization of reconfigurable SET arrays. However, to the best of our knowledge, no mapping approaches that consider the existence of defective nanowire segments were proposed. Thus, this paper presents the first defect-aware approach for mapping reconfigurable SET arrays. The experimental results show that our approach can successfully map the SET arrays with 20% width overhead on average in the presence of 5000 ppm defects. |
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