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The 20th Asia and South Pacific Design Automation Conference

Session 1S  University Design Contest
Time: 10:20 - 12:10 Tuesday, January 20, 2015
Location: Room 103
Chairs: Hiroyuki Ito (Tokyo Inst. of Tech., Japan), Noriyuki Miura (Kobe Univ., Japan)

1S-1 (Time: 10:20 - 10:24)
TitleAn HDL-Synthesized Gated-Edge-Injection PLL with A Current Output DAC
Author*Dongsheng Yang, Wei Deng, Tomohiro Ueno, Teerachot Siriburanon, Satoshi Kondo, Kenichi Okada, Akira Matsuzawa (Tokyo Inst. of Tech., Japan)
Pagepp. 2 - 3
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1S-2 (Time: 10:24 - 10:28)
TitleAn Oscillator-Based True Random Number Generator with Process and Temperature Tolerance
AuthorTakehiko Amaki, *Masanori Hashimoto, Takao Onoye (Osaka Univ., Japan)
Pagepp. 4 - 5
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1S-3 (Time: 10:28 - 10:32)
TitleImplementation of Double Arbiter PUF and Its Performance Evaluation on FPGA
Author*Takanori Machida (Univ. of Electro-Communications, Japan), Dai Yamamoto (Fujitsu Labs., Japan), Mitsugu Iwamoto, Kazuo Sakiyama (Univ. of Electro-Communications, Japan)
Pagepp. 6 - 7
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1S-4 (Time: 10:32 - 10:36)
TitleA Negative-Resistance Sense Amplifier for Low-Voltage Operating STT-MRAM
Author*Yohei Umeki, Koji Yanagida (Kobe Univ., Japan), Shusuke Yoshimoto (Stanford Univ., U.S.A.), Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi (Kobe Univ., Japan), Koji Tsunoda, Toshihiro Sugii (Low-Power Electronics Association and Project (LEAP), Japan)
Pagepp. 8 - 9
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1S-5 (Time: 10:36 - 10:40)
TitleA High Stability, Low Supply Voltage and Low Standby Power Six-Transistor CMOS SRAM
Author*Nobuaki Kobayashi, Ryusuke Ito, Tadayoshi Enomoto (Chuo Univ., Japan)
Pagepp. 10 - 11
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1S-6 (Time: 10:40 - 10:44)
TitleAn Efficient Multi-Port Memory Controller for Multimedia Applications
Author*Xuan-Thuan Nguyen, Cong-Kha Pham (Univ. of Electro-Communications, Japan)
Pagepp. 12 - 13
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1S-7 (Time: 10:44 - 10:48)
TitleReliability-Configurable Mixed-Grained Reconfigurable Array Compatible with High-Level Synthesis
Author*Masanori Hashimoto, Dawood Alnajjar, Hiroaki Konoura (Osaka Univ./JST, CREST, Japan), Yukio Mitsuyama (Kochi Univ. of Tech./JST, CREST, Japan), Hajime Shimada (Nagoya Univ./JST, CREST, Japan), Kazutoshi Kobayashi (Kyoto Inst. of Tech./JST, CREST, Japan), Hiroyuki Kanbara (ASTEM/JST, CREST, Japan), Hiroyuki Ochi (Ritsumeikan Univ./JST, CREST, Japan), Takashi Imagawa (Kyoto Univ./JST, CREST, Japan), Kazutoshi Wakabayashi (NEC/JST, CREST, Japan), Takao Onoye (Osaka Univ./JST, CREST, Japan), Hidetoshi Onodera (Kyoto Univ./JST, CREST, Japan)
Pagepp. 14 - 15
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1S-8 (Time: 10:48 - 10:52)
TitleA 14μA ECG Processor with Noise Tolerant Heart Rate Extractor and FeRAM for Wearable Healthcare Systems
Author*Yozaburo Nakai, Shintaro Izumi, Ken Yamashita, Masanao Nakano, Hiroshi Kawaguchi, Masahiko Yoshimoto (Kobe Univ., Japan)
Pagepp. 16 - 17
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1S-9 (Time: 10:52 - 10:56)
TitleA 128-Way FPGA Platform for the Acceleration of KLMS Algorithm
Author*Xiaowei Ren, Qihang Yu, Badong Chen, Nanning Zheng, Pengju Ren (Xi'an Jiaotong Univ., China)
Pagepp. 18 - 19
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1S-10 (Time: 10:56 - 11:00)
TitleA Real-Time Permutation Entropy Computation for EEG Signals
Author*Xiaowei Ren, Qihang Yu, Badong Chen, Nanning Zheng, Pengju Ren (Xi'an Jiaotong Univ., China)
Pagepp. 20 - 21
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1S-11 (Time: 11:00 - 11:04)
TitleA High Efficient Hardware Architecture for Multiview 3DTV
Author*Jiang Yu, Geng Liu, Xin Zhang, Pengju Ren (Xi'an Jiaotong Univ., China)
Pagepp. 22 - 23
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1S-12 (Time: 11:04 - 11:08)
TitleDesign of A Scalable Many-Core Processor for Embedded Applications
Author*Hsiao-Wei Chien, Jyun-Long Lai, Chao-Chieh Wu, Chih-Tsun Huang, Ting-Shuo Hsu, Jing-Jia Liou (National Tsing Hua Univ., Taiwan)
Pagepp. 24 - 25
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1S-13 (Time: 11:08 - 11:12)
TitleA DPA/DEMA/LEMA-Resistant AES Cryptographic Processor with Supply-Current Equalizer and Micro EM Probe Sensor
Author*Daisuke Fujimoto, Noriyuki Miura (Kobe Univ., Japan), Yu-ichi Hayashi, Naofumi Homma, Takafumi Aoki (Tohoku Univ., Japan), Makoto Nagata (Kobe Univ., Japan)
Pagepp. 26 - 27
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1S-14 (Time: 11:12 - 11:16)
TitleA 6464 1200fps Dual-Mode CMOS Ion-Image Sensor for Accurate DNA Sequencing
Author*Xiwei Huang, Jing Guo, Mei Yan, Hao Yu (Nanyang Technological Univ., Singapore)
Pagepp. 28 - 29
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1S-16 (Time: 11:16 - 11:20)
TitleA 0.21-V Minimum Input, 73.6% Maximum Efficiency, Fully Integrated 3-Terminal Voltage Converter with MPPT for Low-Voltage Energy Harvesters
Author*Toshihiro Ozaki, Tetsuya Hirose, Takahiro Nagai, Keishi Tsubaki, Nobutaka Kuroki, Masahiro Numa (Kobe Univ., Japan)
Pagepp. 30 - 31
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1S-17 (Time: 11:20 - 11:24)
TitleDual-Output Wireless Power Delivery System for Small Size Large Volume Wireless Memory Card
Author*Junki Hashiba, Toru Kawajiri, Yuya Hasegawa, Hiroki Ishikuro (Keio Univ., Japan)
Pagepp. 32 - 33
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1S-18 (Time: 11:24 - 11:28)
TitleA Tri-Level 50MS/s 10-bit Capacitive-DAC for Bluetooth Applications
Author*Daisuke Kanemoto (Univ. of Yamanashi, Japan), Keigo Oshiro, Keiji Yoshida, Haruichi Kanaya (Kyushu Univ., Japan)
Pagepp. 34 - 35
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1S-19 (Time: 11:28 - 11:32)
TitleA Tail-Current Modulated VCO with Adaptive-Bias Scheme
Author*Aravind Tharayil Narayanan, Wei Deng, Kenichi Okada, Akira Matsuzawa (Tokyo Inst. of Tech., Japan)
Pagepp. 36 - 37
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1S-20 (Time: 11:32 - 11:36)
TitleA Low-Power VCO Based ADC with Asynchronous Sigma-Delta Modulator in 65nm CMOS
Author*Jili Zhang, Chenluan Wang, Shengxi Diao, Fujiang Lin (Univ. of Science and Tech. of China, China)
Pagepp. 38 - 39
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1S-21 (Time: 11:36 - 11:40)
TitleA 0.5-V 5.8-GHz Low-Power Asymmetrical QPSK/OOK Transceiver for Wireless Sensor Network
Author*Sho Ikeda, Sang_yeop Lee, Shin Yonezawa, Yiming Fang, Motohiro Takayasu, Taisuke Hamada, Yosuke Ishikawa, Hiroyuki Ito, Noboru Ishihara, Kazuya Masu (Tokyo Inst. of Tech., Japan)
Pagepp. 40 - 41
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1S-22 (Time: 11:40 - 11:44)
TitleA 58.3-to-65.4 GHz 34.2 mW Sub-Harmonically Injection-Locked PLL with a Sub-Sampling Phase Detection
Author*Teerachot Siriburanon, Tomohiro Ueno, Kento Kimura, Satoshi Kondo, Wei Deng, Kenichi Okada, Akira Matsuzawa (Tokyo Inst. of Tech., Japan)
Pagepp. 42 - 43
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1S-23 (Time: 11:44 - 11:48)
TitleCircuit and Package Design for 44GB/s Inductive-Coupling DRAM/SoC Interface
Author*Akira Okada, Abdul Raziz Junaidi, Yasuhiro Take, Atsutake Kosuge, Tadahiro Kuroda (Keio Univ., Japan)
Pagepp. 44 - 45
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1S-24 (Time: 11:48 - 11:52)
TitleDesign and Analysis for ThruChip Design for Manufacturing (DFM)
Author*Li-Chung Hsu, Yasuhiro Take, Atsutake Kosuge, So Hasegawa, Junichiro Kadamoto, Tadahiro Kuroda (Keio Univ., Japan)
Pagepp. 46 - 47
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