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The 20th Asia and South Pacific Design Automation Conference

Session 1S  University Design Contest
Time: 10:20 - 12:10 Tuesday, January 20, 2015
Location: Room 103
Chairs: Hiroyuki Ito (Tokyo Institute of Technology, Japan), Noriyuki Miura (Kobe University, Japan)

1S-1 (Time: 10:20 - 10:24)
TitleAn HDL-Synthesized Gated-Edge-Injection PLL with A Current Output DAC
Author*Dongsheng Yang, Wei Deng, Tomohiro Ueno, Teerachot Siriburanon, Satoshi Kondo, Kenichi Okada, Akira Matsuzawa (Tokyo Institute of Technology, Japan)
Pagepp. 2 - 3
KeywordSynthesizable, Logic synthesis, ADPLL, Gated edge injection, Standard cell
AbstractThis paper presents a small area, low power, fully synthesizable PLL with a current output DAC and an interpolative-phase coupled oscillator using edge injection technique for on-chip clock generation. A prototype PLL is fabricated in a 65nm digital CMOS process, achieves a 1.7-ps integrated jitter at 0.9 GHz and consumes 0.78 mW leading to an FOM of -236.5 dB while only occupying an area of 0.0066 mm2. It achieves the best performance-area trade-off.
Slides

1S-2 (Time: 10:24 - 10:28)
TitleAn Oscillator-Based True Random Number Generator with Process and Temperature Tolerance
AuthorTakehiko Amaki, *Masanori Hashimoto, Takao Onoye (Osaka University, Japan)
Pagepp. 4 - 5
Keywordtrule random number generator, process variation, temperature fluctuation
AbstractThis paper presents an oscillator-based true random number generator (TRNG) that automatically adjusts the duty cycle of a fast oscillator to 50 %, and generates unbiased random numbers tolerating process variation and dynamic temperature fluctuation. Measurement results with 65nm test chips show that the proposed TRNG adjusted the probability of ‘1’ to within 50 ± 0.07 % in five chips in the temperature range of 0 ℃ to 75 ℃. Consequently, the proposed TRNG passed the NIST and DIEHARD tests at 7.5 Mbps with 6,670 μm2 area.
Slides

1S-3 (Time: 10:28 - 10:32)
TitleImplementation of Double Arbiter PUF and Its Performance Evaluation on FPGA
Author*Takanori Machida (The University of Electro-Communications, Japan), Dai Yamamoto (Fujitsu Laboratories Ltd., Japan), Mitsugu Iwamoto, Kazuo Sakiyama (The University of Electro-Communications, Japan)
Pagepp. 6 - 7
KeywordArbiter-based PUF, FPGA, Equal-length wiring, Uniqueness, Machine-learning attacks
AbstractLow uniqueness and vulnerability to machine-learning attacks are known as two major problems of Arbiter-Based Physically Unclonable Function (APUF) implemented on FPGAs. In this paper, we implement Double APUF (DAPUF) that duplicates the original APUF in order to overcome the problems. From the experimental results on Xilinx Virtex-5, we show that the uniqueness of DAPUF becomes almost ideal, and the prediction rate of the machine-learning attack decreases from 86% to 57%.

1S-4 (Time: 10:32 - 10:36)
TitleA Negative-Resistance Sense Amplifier for Low-Voltage Operating STT-MRAM
Author*Yohei Umeki, Koji Yanagida (Graduate School of System Informatics, Kobe University, Japan), Shusuke Yoshimoto (Department of Electrical Engineering, Stanford University, U.S.A.), Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi (Graduate School of System Informatics, Kobe University, Japan), Koji Tsunoda, Toshihiro Sugii (Low-Power Electronics Association and Project (LEAP), Japan)
Pagepp. 8 - 9
KeywordLow-voltage, STT-MRAM, Non-volatile memory
AbstractThis paper exhibits a 65-NM 8-Mb spin transfer torque magnetoresistance random access memory (STT-MRAM) operating at 0.38V. The proposed sense amplifier comprises a boosted-gate nMOS and negative-resistance pMOSes as loads, which maximizes the readout margin. The STT-MRAM achieves a cycle time of 1.9 μs (= 0.526 MHz) at 0.38 V. The operating power is 1.70 μW at that voltage.
Slides

1S-5 (Time: 10:36 - 10:40)
TitleA High Stability, Low Supply Voltage and Low Standby Power Six-Transistor CMOS SRAM
Author*Nobuaki Kobayashi, Ryusuke Ito, Tadayoshi Enomoto (Chuo University, Japan)
Pagepp. 10 - 11
KeywordCMOS, SRAM, Standby Power Dissipation, Self-controllable Voltage Level (SVL) Circuit
AbstractStatic random access memories (SRAMs) having high “read” and “write” margins, and a small standby power (PST) are needed for use in low supply voltage battery-driven portable systems. The decrease in MOSFET sizes increases not only leakage currents, but also threshold voltage variation that results in smaller margins[1], [2]. To solve these problems a very small circuit called a “Self-controllable Voltage Level (SVL)” circuit[3] was used in the newly developed (dvlp.) SRAM. The dvlp. SRAM succeeded in increasing margins, reducing the standby power and lowering a supply voltage (VDD). The PST of the 2-kbit-memory cell array of the dvlp. SRAM was only 0.938 μW, namely, 9.17% of PST (10.23 µW) of the conventional (conv.) SRAM at VDD=1.0 V. A “read” margin (VRM) of the dvlp. SRAM was 0.1923 V that was 2.09 times larger than VRM (0.0919 V) of the conv. SRAM at VDD=1.0 V.
Slides

1S-6 (Time: 10:40 - 10:44)
TitleAn Efficient Multi-Port Memory Controller for Multimedia Applications
Author*Xuan-Thuan Nguyen, Cong-Kha Pham (University of Electro-Communications, Japan)
Pagepp. 12 - 13
Keywordmulti-port memory controller, high bandwidth, fpga, multimedia
AbstractThe remedy for processor-memory bottleneck has considered as the key to success because of the substantial growth in multimedia applications. In this paper, an efficient external multi-port memory controller (MPMC) which consists of several buffers to speed up the transactions, embedded memory to store the configuration, and an arbiter to schedule all access, is proposed. The experimental results prove that the proposed design can operate independently of other system architectures, support up to 16 simultaneous external components with different clocks and data width, and achieve up to 88% and 92% of theory peak bandwidth for write and read process, respectively.

1S-7 (Time: 10:44 - 10:48)
TitleReliability-Configurable Mixed-Grained Reconfigurable Array Compatible with High-Level Synthesis
Author*Masanori Hashimoto, Dawood Alnajjar, Hiroaki Konoura (Osaka University/JST, CREST, Japan), Yukio Mitsuyama (Kochi University of Technology/JST, CREST, Japan), Hajime Shimada (Nagoya University/JST, CREST, Japan), Kazutoshi Kobayashi (Kyoto Institute of Technology/JST, CREST, Japan), Hiroyuki Kanbara (ASTEM/JST, CREST, Japan), Hiroyuki Ochi (Ritsumeikan University/JST, CREST, Japan), Takashi Imagawa (Kyoto University/JST, CREST, Japan), Kazutoshi Wakabayashi (NEC Corp./JST, CREST, Japan), Takao Onoye (Osaka University/JST, CREST, Japan), Hidetoshi Onodera (Kyoto University/JST, CREST, Japan)
Pagepp. 14 - 15
Keywordreconfigurable device, soft error, high-level synthesis, reliability, irradiation test
AbstractThis paper presents a mixed-grained reconfigurable VLSI array architecture that can cover mission-critical applications to consumer products through C-to-array application mapping. A proof-of-concept VLSI chip was fabricated in a 65nm process. Measurement results show that applications on the chip can be working in a harsh radiation environment.
Slides

1S-8 (Time: 10:48 - 10:52)
TitleA 14μA ECG Processor with Noise Tolerant Heart Rate Extractor and FeRAM for Wearable Healthcare Systems
Author*Yozaburo Nakai, Shintaro Izumi, Ken Yamashita, Masanao Nakano, Hiroshi Kawaguchi, Masahiko Yoshimoto (Kobe University, Japan)
Pagepp. 16 - 17
Keywordbiomedical signal processing, electrocardiography, heart rate extraction, mobile healthcare, wearable sensors
AbstractThis report describes an electrocardiograph (ECG) processor for use with a wearable healthcare system. It comprises an analog front end, a 12-bit ADC, a robust Instantaneous Heart Rate (IHR) monitor, a 32-bit Cortex-M0 core, and 64 Kbyte Ferroelectric Random Access Memory (FeRAM). The IHR monitor uses a short-term autocorrelation (STAC) algorithm to improve the heart-rate detection accuracy despite its use in noisy conditions. The ECG processor chip consumes 13.7μA for heart rate logging application.
Slides

1S-9 (Time: 10:52 - 10:56)
TitleA 128-Way FPGA Platform for the Acceleration of KLMS Algorithm
Author*Xiaowei Ren, Qihang Yu, Badong Chen, Nanning Zheng, Pengju Ren (Xi'an Jiaotong University, China)
Pagepp. 18 - 19
KeywordKLMS, FPGA, parallel, acceleration
AbstractThis paper proposes a 128-way parallel FPGA platform to accelerate the kernel least mean square (KLMS) algorithm. With the adoption of a quantized method and pipeline technology, this platform which works at 200MHz is 4827 times faster, on average, than the Matlab code running on a 3GHz Intel(R) Core(TM) i5-2320 CPU.
Slides

1S-10 (Time: 10:56 - 11:00)
TitleA Real-Time Permutation Entropy Computation for EEG Signals
Author*Xiaowei Ren, Qihang Yu, Badong Chen, Nanning Zheng, Pengju Ren (Xi'an Jiaotong University, China)
Pagepp. 20 - 21
KeywordPermutation Entropy, FPGA, parallel, acceleration
AbstractIn this paper, we implement a reconfigurable FPGA accelerator which could compute multiscale permutation entropy for 128 EEG signals simultaneously in real time. When it works at 150MHz and the window size is 256, compared with C code running on a 3GHz Intel(R) Core(TM) i5-2320 CPU, the average speedup is 3748.
Slides

1S-11 (Time: 11:00 - 11:04)
TitleA High Efficient Hardware Architecture for Multiview 3DTV
Author*Jiang Yu, Geng Liu, Xin Zhang, Pengju Ren (Institute of Artifical Intelligence and Robotics, Xi'an Jiaotong University, China)
Pagepp. 22 - 23
Keyword3DTV, Architecture, FPGA, Multiview
AbstractThere are three main challenges to design an efficient multiview 3DTV SoC: (1)how to organize DRAM address mapping to maximize off-chip bandwidth utilization; (2)how to design a parallel configurable image scaling engine to interpolate various viewpoints in real-time; (3)how to reduce computational complexity of float-point sub-pixel rearrangement with sufficient accuracy. To this end, we present a highly optimized hardware architecture, which saves 38.4% logic and 37.5% memory resources when implementing a multiview 1080P@60Hz 3DTV on the Xilinx XC5VLX330 FPGA.
Slides

1S-12 (Time: 11:04 - 11:08)
TitleDesign of A Scalable Many-Core Processor for Embedded Applications
Author*Hsiao-Wei Chien, Jyun-Long Lai, Chao-Chieh Wu, Chih-Tsun Huang, Ting-Shuo Hsu, Jing-Jia Liou (National Tsing Hua University, Taiwan)
Pagepp. 24 - 25
KeywordMany-Core, Hardware/Software Co-Validation
AbstractWe present a novel design of scalable many-core processor with its comprehensive development framework, including the Electronic System Level, Register Transfer Level, and full-system prototyping platforms. Architecture exploration, performance evaluation and system verification/validation can be done across different abstraction levels. With our hardware-independent software layer, applications built on top of the fast virtual platform can be executed seamlessly on the prototype. The emulation result justifies the effectiveness of our processor architecture in embedded applications.

1S-13 (Time: 11:08 - 11:12)
TitleA DPA/DEMA/LEMA-Resistant AES Cryptographic Processor with Supply-Current Equalizer and Micro EM Probe Sensor
Author*Daisuke Fujimoto, Noriyuki Miura (Kobe University, Japan), Yu-ichi Hayashi, Naofumi Homma, Takafumi Aoki (Tohoku University, Japan), Makoto Nagata (Kobe University, Japan)
Pagepp. 26 - 27
KeywordAES, side-channel attack, EM attack, power equalizer, sensor
AbstractCombination of a supply-current equalizer (EQ) and a micro EM probe sensor (EMS) exhibits strong resiliency against major three DPA/DEMA/LEMA low-cost side-channel attacks on a cryptographic processor. Test-chip measurements with 128bit AES cryptographic processor in 0.18um CMOS successfully demonstrate the secret key protection from all three attacks. A digital-oriented circuit implementation together with a careful design optimization minimizes the hardware overhead of EQ and EMS to +33%, +1.6% in area, +7.6%, +0.15% in power, and ~0%, -0.2% in performance of an unprotected AES, respectively.

1S-14 (Time: 11:12 - 11:16)
TitleA 64×64 1200fps Dual-Mode CMOS Ion-Image Sensor for Accurate DNA Sequencing
Author*Xiwei Huang, Jing Guo, Mei Yan, Hao Yu (Nanyang Technological University, Singapore)
Pagepp. 28 - 29
KeywordCIS, ISFET, pH detection, contact imaging, DNA sequencing
AbstractA dual-mode CMOS ion-image sensor is demonstrated towards accurate high-throughput DNA sequencing. Dual-mode (optical/pH) sensing is realized by integrating the ion-sensitive field-effect transistor (ISFET) with standard 4T CMOS image sensor (CIS) pixel fabricated in standard 0.18μm CIS process. With accurate determination of microbead physical locations by optical contact imaging, local pH can be obtained for one DNA slice with accurate correlation to improve sequencing accuracy from system perspective. Moreover, for high-throughput large-arrayed sequencing, pixel-to-pixel ISFET threshold voltage mismatch is reduced by a correlated double sampling (CDS) readout that supports both image and pH modes. Measurement results show a sensitivity of 103.8mV/pH, a fixed-pattern-noise (FPN) reduction from 4% to 0.3%, and a readout speed of 1200 frames/second (fps).
Slides

1S-16 (Time: 11:16 - 11:20)
TitleA 0.21-V Minimum Input, 73.6% Maximum Efficiency, Fully Integrated 3-Terminal Voltage Converter with MPPT for Low-Voltage Energy Harvesters
Author*Toshihiro Ozaki, Tetsuya Hirose, Takahiro Nagai, Keishi Tsubaki, Nobutaka Kuroki, Masahiro Numa (Kobe University, Japan)
Pagepp. 30 - 31
KeywordEnergy harvesting, voltage converter, low-voltage, low-power
AbstractWe propose a fully integrated 3-terminal voltage converter with a maximum power point tracking (MPPT) circuit for low-voltage energy harvesting. The MPPT circuit dissipates nano-watt power to extract maximum output power. The measurement results demonstrated that the circuit converted a 0.49-V input to a 1.46-V output with 73.6% power conversion efficiency when the output power was 348 uW. The circuit can operate at an extremely low input voltage of 0.21 V.
Slides

1S-17 (Time: 11:20 - 11:24)
TitleDual-Output Wireless Power Delivery System for Small Size Large Volume Wireless Memory Card
Author*Junki Hashiba, Toru Kawajiri, Yuya Hasegawa, Hiroki Ishikuro (Keio University, Japan)
Pagepp. 32 - 33
Keywordwireless power delivery, single-inductor dual-output, Pseudo-random-sequence PWM
AbstractA single-inductor dual-output wireless power delivery system for small size battery-less NAND flash memory card is presented. The power delivery system uses two rectifiers connected to a single inductor which is synchronously switched by pseudo-random-sequence PWM signal with induced AC voltage. The power delivery system can generate 8 V and 16 V with peak efficiency of 40 % and maximum total transmitting power is 0.5 W. The test chip was designed and fabricated using 0.18um-CMOS with high-voltage LDMOS option.
Slides

1S-18 (Time: 11:24 - 11:28)
TitleA Tri-Level 50MS/s 10-bit Capacitive-DAC for Bluetooth Applications
Author*Daisuke Kanemoto (University of Yamanashi, Japan), Keigo Oshiro, Keiji Yoshida, Haruichi Kanaya (Kyushu University, Japan)
Pagepp. 34 - 35
KeywordCapacitive, DAC
AbstractThis document summarizes, for the university design contest, a chip design of low power dissipation and small die area 10-bit capacitive digital-to-analog converter (DAC) in a 0.18 um CMOS process. Power dissipation of this chip is 350 uW including the output buffers. The die area is 0.081mm2

1S-19 (Time: 11:28 - 11:32)
TitleA Tail-Current Modulated VCO with Adaptive-Bias Scheme
Author*Aravind Tharayil Narayanan, Wei Deng, Kenichi Okada, Akira Matsuzawa (Tokyo Institute of Technology, Japan)
Pagepp. 36 - 37
KeywordVCO, Class-C, PVT, flicker noise
AbstractThis paper proposes a tail-current modulated VCO with adaptive-bias scheme. The proposed adaptive-bias scheme ensures robust startup conditions for the tail-feedback VCO. A tail-feedback VCO using the proposed scheme is implemented in a 0.18-μm CMOS process. The measured phase noise is -119.3dBc/Hz at 1MHz offset with a power dissipation of 6.8mW at 4.6GHz.
Slides

1S-20 (Time: 11:32 - 11:36)
TitleA Low-Power VCO Based ADC with Asynchronous Sigma-Delta Modulator in 65nm CMOS
Author*Jili Zhang, Chenluan Wang, Shengxi Diao, Fujiang Lin (University of Science and Technology of China, China)
Pagepp. 38 - 39
KeywordVCO, ADC, ASDM, Nonlinearity
AbstractThis paper presents a low power VCO based ADC with asynchronous sigma-delta modulator (ASDM). A prototype is designed in 65nm CMOS technology with a measured performance of 54.3dB SNDR and 68dB SFDR over 8MHz bandwidth while consuming 2.8mW from a 1.2V supply.
Slides

1S-21 (Time: 11:36 - 11:40)
TitleA 0.5-V 5.8-GHz Low-Power Asymmetrical QPSK/OOK Transceiver for Wireless Sensor Network
Author*Sho Ikeda, Sang_yeop Lee, Shin Yonezawa, Yiming Fang, Motohiro Takayasu, Taisuke Hamada, Yosuke Ishikawa, Hiroyuki Ito, Noboru Ishihara, Kazuya Masu (Tokyo Institute of Technology, Japan)
Pagepp. 40 - 41
KeywordTransceiver, PLL, VCO, 0.5V
AbstractThis paper proposes low power RF transceiver which is suitable for wireless sensor network. Using 5.8GHz band has potentiality to achieve small size wireless sensor module because of smaller antenna in higher frequency. The proposed transceiver utilizes different modulation schemes for uplink and downlink to optimize power consumption and spectral efficiency. In addition, supply voltage of 0.5V can reduce the power consumption of overall RF transceiver. The prototype transceiver was fabricated in 65nm CMOS process, and the transmitter achieved EVM of 12.6% while consuming 2.86mW, and the receiver realizes sensitivity of -75dBm while consuming 0.83mW.
Slides

1S-22 (Time: 11:40 - 11:44)
TitleA 58.3-to-65.4 GHz 34.2 mW Sub-Harmonically Injection-Locked PLL with a Sub-Sampling Phase Detection
Author*Teerachot Siriburanon, Tomohiro Ueno, Kento Kimura, Satoshi Kondo, Wei Deng, Kenichi Okada, Akira Matsuzawa (Tokyo Institute of Technology, Japan)
Pagepp. 42 - 43
KeywordPLL, sub-sampling, mm-wave, 60GHz, in-band phase noise
AbstractThis paper presents a low power and low noise sub-harmonically injection-locked PLL based on a 20GHz sub-sampling PLL (SS-PLL) and a quadrature injection locked oscillator (QILO). Relatively lower in-band phase noise and out-of-band phase noise have been achieved through the sub-sampling phase detection and sub-harmonic injection techniques, respectively. Implemented in a 65nm CMOS process, this work can support all 60GHz channels and achieves a phase noise of -115dBc/Hz at 10MHz offset while consuming 20.2mW and 14mW from the 20GHz SS-PLL and the QILO, respectively.

1S-23 (Time: 11:44 - 11:48)
TitleCircuit and Package Design for 44GB/s Inductive-Coupling DRAM/SoC Interface
Author*Akira Okada, Abdul Raziz Junaidi, Yasuhiro Take, Atsutake Kosuge, Tadahiro Kuroda (Keio University, Japan)
Pagepp. 44 - 45
KeywordTCI, phase division multiplexing, UT-FOWLP
AbstractA 44GB/s inductive-coupling DRAM/SoC interface is developed by PoP configuration. It utilizes the advantages of both TSV and LPDDR by using the ThruChip Interface (TCI) and the ultra-thin fan-out wafer level package (UT-FOWLP). This proposed interface outperforms WIO2 with TSV in terms of area efficiency (4x better), immunity from simultaneous switching output noise (32x better) and manufacturing cost (40% cheaper). In addition, it outperforms LPDDR4 in PoP in terms of power dissipation (5x lower) and timing control easiness.
Slides

1S-24 (Time: 11:48 - 11:52)
TitleDesign and Analysis for ThruChip Design for Manufacturing (DFM)
Author*Li-Chung Hsu, Yasuhiro Take, Atsutake Kosuge, So Hasegawa, Junichiro Kadamoto, Tadahiro Kuroda (Keio University, Japan)
Pagepp. 46 - 47
KeywordThruChip, TCI, DFM
AbstractA 1GB/s ThruChip interface (TCI) test chip for wafer thinning, power mesh, and dummy metal fill impacts are analyzed and evaluated with test chip measurement and field solver simulation. The measurement results show that TCI coil dimension can be sized down as wafer thinning by following D/Z=3 rule. However, the experiment shows 20% power reduction by enlarging TCI coil (D/Z=6). The power mesh lies between TCI coils can dramatically decrease the TCI magnetic pulse strength and hence cause TCI to fail. Dummy metal within TCI coils has no impact on TCI transmission.
Slides