| Title | Nonvolatile Memory Allocation and Hierarchy Optimization for High-Level Synthesis |
| Author | Shuangchen Li (Tsinghua University, China/University of California, Santa Barbara, U.S.A.), Ang Li, Yongpan Liu (Tsinghua University, China), *Yuan Xie (University of California, Santa Barbara, U.S.A.), Huazhong Yang (Tsinghua University, China) |
| Page | pp. 166 - 171 |
| Keyword | nonvolatile memory, high-level synthesis, emerging technology, system-level optimization |
| Abstract | The emerging nonvolatile memory (NVM) technology can potentially change the landscape of future IC designs with numerous benefits, such as high performance, instant on/off, ultra-low standby leakage power, and data retention. These advantages motivate designers to exploit utilizing NVM in application-specific circuit designs. The NVM architecture in ASIC and FPGA, however, is quite different from the conventional memory architecture in microprocessors. It is distributed and needs optimization for specific memory access patterns. Furthermore, unique challenges, such as large write energy, asymmetric read/write operations and so on, lead to extra design knobs. This paper focuses on the NVM allocation and hierarchy optimization in high-level synthesis. This is the first framework that integrates the NVM architectures in high-level synthesis. A hierarchical hybrid memory architecture is presented. The NVM architecture optimization decides the memory hierarchy, type (NVM or SRAM) and capacity. It is formulated as a mixed-integer linear programming (MILP) problem. In addition, a branch-and-bound heuristic is developed to handle the cases when the MILP is too costly. Experimental results on real world benchmarks demonstrate that both of the solutions reduce power consumption up to 69.3% under given performance/area constraints, compared with traditional designs without NVM. |
| Title | Reverse BDD-Based Synthesis for Splitter-Free Optical Circuits |
| Author | Robert Wille, *Oliver Keszocze, Clemens Hopfmuller, Rolf Drechsler (University of Bremen, Germany) |
| Page | pp. 172 - 177 |
| Keyword | synthesis, optical circuits, binary decision diagrams, splitter |
| Abstract | With the advancements in silicon photonics, optical devices have found applications e.g. for ultra-high speed and low-power interconnects as well as functional computations to be realized on-chip. Caused by the increasing complexity of the underlying functionality, also the need for computer-aided design methods for this technology rises. Motivated by that, initial work on the development of synthesis methods for optical circuits has been performed. But all approaches proposed thus far suffer e.g. from large synthesis results and restricted scalability. In particular, splittings in the resulting circuits which degrade the optical signals into hardly measureable fractions prevent an efficient and scalable synthesis for optical circuits. In this work, we present a synthesis approach based on Binary Decision Diagrams (BDDs) that overcomes these obstacles. The approach yields circuits that rely on a total of none splitters – at the expense of a moderate increase in the number of optical gates. Experiments confirm that, by this, an efficient and scalable synthesis scheme for optical circuits eventually becomes available. |
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| Title | Determining the Minimal Number of SWAP Gates for Multi-Dimensional Nearest Neighbor Quantum Circuits |
| Author | Aaron Lye (University of Bremen, Germany), *Robert Wille, Rolf Drechsler (University of Bremen/Cyber Physical Systems, DFKI GmbH, Germany) |
| Page | pp. 178 - 183 |
| Keyword | optimization, quantum circuits, nearest neighbor, exact, synthesis |
| Abstract | Motivated by the promises of significant speed-ups for certain problems, quantum computing received significant attention in the past. While much progress has been made in the development of synthesis methods for quantum circuits, new physical developments constantly lead to new constraints to be addressed. The limited interaction distance between the respective qubits (i.e. nearest neighbor optimization) has already been considered intensely. But with the emerge of multi-dimensional quantum architectures, another physical constraint came up for which only a few automatic synthesis solutions exist yet – all of them of heuristic nature. In this work, we propose an exact scheme for nearest neighbor optimization in multidimensional quantum circuits. Although the complexity of the problem is a serious obstacle, our experimental evaluation shows that the proposed solution is sufficient to allow for a qualitative evaluation of the respective optimization steps. At the same time, this enabled an exact comparison to heuristical results for the first time. |
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