| Title | Aging Mitigation in Memory Arrays Using Self-Controlled Bit-Flipping Technique |
| Author | *Anteneh Gebregiorgis (TU Delft, Netherlands), Mojtaba Ebrahimi, Saman Kiamehr, Fabian Oboril (Karlsruhe Institute of Technology, Germany), Said Hamdioui (TU Delft, Netherlands), Mehdi Tahoori (Karlsruhe Institute of Technology, Germany) |
| Page | pp. 231 - 236 |
| Keyword | Aging, Relibility |
| Abstract | By downscaling CMOS technologies into the
nanometer regime, the reliability of SRAM memories is threatened
by accelerated transistor aging mechanisms such as Bias
Temperature Instability (BTI). BTI leads to a considerable degradation
of SRAM cell Static Noise Margin (SNM), which increases
the memory failure rate. Since BTI is workload dependent, the
aging rates of different cells in a memory array are quite nonuniform.
To address this issue, a variety of bit-flipping techniques
has been proposed to decrease the SNM degradation by balancing
the signal probabilities of the cells. However, existing bit-flipping
techniques impose too much area and power overhead as at least
an additional column is required to store the inversion flags.
In this paper, we propose a low cost self-controlled bit-flipping
technique which inverts all bit positions with respect to an existing
bit. This technique is applied to a register-file and cache units of
an embedded microprocessor. Our simulation results show that
the reliability of the proposed technique is similar to that of
existing bit-flipping techniques, while imposing 64% less area
overhead. |
| Title | Design Methodology for Approximate Accumulator Based on Statistical Error Model |
| Author | Chang Liu, *Xinghua Yang, Fei Qiao, Qi Wei, Huazhong Yang (Dept.of Electronic Engineering, Tsinghua University, China) |
| Page | pp. 237 - 242 |
| Keyword | approximate-computing, statistical model, multistage speculative adder |
| Abstract | Approximate computing technology has aroused
growing interest in circuit and system design for its wellperformed
tradeoff between output quality and performance.
Numerous basic circuits and system design methodologies for
approximate computing have been proposed. Considering that
the existing methodologies for the evaluation of tradeoff between
output quality and performance is time-consuming, this paper
presents a fast design methodology for approximate accumulator
based on statistical error models, in which the inexact multistage
speculative adder is adopted and modeled for its advantage
of compact error patterns. To validate the proposed methodology,
Support Vector Machine(SVM) algorithm is analyzed
and mapped to a hardware system composed of inexact and
accurate computing circuits. Results show that our time for
searching the optimal mapping circuits has been saved by 22.08%
than functional-based simulation where the final approximate
system design achieves 1.57× speedups with 8.56% accuracy
degradation. |
| Slides |