| Title | Multiple Independent Gate FETs: How Many Gates Do We Need? |
| Author | *Luca Amaru (Integrated Systems Laboratory - EPFL, Switzerland), Gage Hills (Stanford Univ., U.S.A.), Pierre-Emmanuel Gaillardon (Integrated Systems Laboratory - EPFL, Switzerland), Subhasish Mitra (Stanford Univ., U.S.A.), Giovanni De Micheli (Integrated Systems Laboratory - EPFL, Switzerland) |
| Page | pp. 243 - 248 |
| Detailed information (abstract, keywords, etc) | |
| Slides | |
| Title | Polynomial Time Algorithm for Area and Power Efficient Adder Synthesis in High-Performance Designs |
| Author | Subhendu Roy (Univ. of Texas, Austin, U.S.A.), Mihir Choudhury, Ruchir Puri (IBM, U.S.A.), *David Z Pan (Univ. of Texas, Austin, U.S.A.) |
| Page | pp. 249 - 254 |
| Detailed information (abstract, keywords, etc) | |
| Title | Accelerating SAT-Based Boolean Matching for Heterogeneous FPGAs Using One-Hot Encoding and CEGAR Technique |
| Author | *Yusuke Matsunaga (Kyushu Univ., Japan) |
| Page | pp. 255 - 260 |
| Detailed information (abstract, keywords, etc) | |