| Title | Multiple Independent Gate FETs: How Many Gates Do We Need? |
| Author | *Luca Amaru (Integrated Systems Laboratory - EPFL, Switzerland), Gage Hills (Robust Systems Group - Stanford University, U.S.A.), Pierre-Emmanuel Gaillardon (Integrated Systems Laboratory - EPFL, Switzerland), Subhasish Mitra (Robust Systems Group - Stanford University, U.S.A.), Giovanni De Micheli (Integrated Systems Laboratory - EPFL, Switzerland) |
| Page | pp. 243 - 248 |
| Keyword | MIGFET, Logic Synthesis, Emerging Devices, Enhanced Functionality, CAD |
| Abstract | Multiple Independent Gate Field Effect Transistors (MIGFETs) are expected to push FET technology further into the semiconductor roadmap. In a MIGFET, supplementary gates either provide (i) enhanced conduction properties or (ii) more in- telligent switching functions. In general, each additional gate also introduces a side implementation cost. To enable more efficient digital systems, MIGFETs must leverage their expressive power to realize complex logic circuits with few physical resources. Researchers face then the question: How many gates do we need? In this paper, we address the logic side of this question. We determine whether or not an increasing number of gates leads to more compact logic implementations. For this purpose, we develop a logic synthesis flow that intrisically exploits a MIGFET switching function. Using simplified design assumptions and device/interconnect models, we synthesize MCNC benchmarks on 5 promising MIGFET devices, with number of gates ranging from 1 to 7. Experimental results evidence nontrivial area/delay/energy minima, located between 1 and 4 gates, depending on a MIGFET switching function and device/interconnect technology. |
| Slides |
| Title | Polynomial Time Algorithm for Area and Power Efficient Adder Synthesis in High-Performance Designs |
| Author | Subhendu Roy (The University of Texas at Austin, U.S.A.), Mihir Choudhury, Ruchir Puri (IBM T J Watson Research Center, U.S.A.), *David Z Pan (The University of Texas at Austin, U.S.A.) |
| Page | pp. 249 - 254 |
| Keyword | Parallel prefix adder, Polynomial algorithm, logic synthesis |
| Abstract | Adders are the most fundamental arithmetic units, and often
on the timing critical paths of microprocessors. Among var-
ious adder configurations, parallel prefix structures provide
the high performance adders for higher bit-widths. With
aggressive technology scaling, the performance of a paral-
lel prefix adder, in addition to the dependence on the logic-
level, is determined by wire-length and congestion which can
be mitigated by adjusting fan-out. This paper proposes a
polynomial-time algorithm to synthesize n bit parallel pre-
fix adders targeting the minimization of the size of the pre-
fix graph with log2 n logic level and any arbitrary fan-out
restriction. The design space exploration by our algorithm
provides a set of pareto-optimal solutions for delay vs. power
trade-off, and these pareto-optimal solutions can be used in
high-performance designs instead of picking from a fixed li-
brary (Kogge Stone, Sklansky etc.). Experimental results
demonstrate that our approach (i) excels highly competi-
tive industry standard Synopsys Design Compiler adder (128
bit) in performance (2%), area (25%) and power (13.3%) in
32nm technology node, and (ii) improves performance/area
over even 64 bit custom designed adders targeting 22nm
technology library and implemented in an industrial high-
performance design. |
| Title | Accelerating SAT-Based Boolean Matching for Heterogeneous FPGAs Using One-Hot Encoding and CEGAR Technique |
| Author | *Yusuke Matsunaga (Kyushu University, Japan) |
| Page | pp. 255 - 260 |
| Keyword | FPGA, technology mapping, SAT solver, CEGAR |
| Abstract | This paper describes two speed-up techniques for Boolean
matching of LUT-based circuits. One is one-hot encoding technique
for variables representing input assignments. Though
it requires more variables than existing binary encoding technique,
almost all added clauses using one-hot encoding are
binary clauses, which are suitable for efficient Boolean constraint
propagation. The other is CEGAR (counter example
guided abstraction refinement) technique which reduces the
CPU time significantly. With both techniques, we can solve
Boolean matching problem with 9 input function in 20 milliseconds
on average, which is faster than the existing algorithms
more than one order of magnitude. |