| Title | Checkpoint-Aware Instruction Scheduling for Nonvolatile Processor with Multiple Functional Units |
| Author | Mimi Xie, Chen Pan, *Jingtong Hu (Oklahoma State University, U.S.A.), Chengmo Yang (University of Delaware, U.S.A.), Yiran Chen (University of Pittsburgh, U.S.A.) |
| Page | pp. 316 - 321 |
| Keyword | Nonvolatile registers, FRAM, Energy, Writes |
| Abstract | Embedded systems powered with harvested energy experience frequent execution interruption due to unstable energy source. Nonvolatile (NV) register based processor is proposed to realize fast resume after power failure. The states in the volatile registers are checkpointed to NV registers. However, frequent checkpointing causes performance degradation and consumes excessive power. In this paper, we propose the checkpoint aware instruction scheduling (CAIS) algorithm to reduce the writes to NV registers. Experiments show that CAIS can improve performance and reduce power consumption. |
| Slides |
| Title | Balloonfish: Utilizing Morphable Resistive Memory in Mobile Virtualization |
| Author | Linbo Long, Duo Liu, *Xiao Zhu, Kan Zhong (Chongqing University, China), Zili Shao (The Hong Kong Polytechnic University, Hong Kong), Edwin H.-M. Sha (Chongqing University, China) |
| Page | pp. 322 - 327 |
| Keyword | mobile virtualization, phase change memory, Morphable Resistive Memory, page allocation |
| Abstract | Virtualization offers significant benefits such as better isolation and security for mobile systems. However, the limited amount of memory and virtualization's memory-demanding nature makes it challenging to virtualize mobile systems efficiently. In this paper, we utilize morphable resistive memories to design a high-performance mobile system with extensible memory space. With morphable resistive memory, we convert the memory cell state between multi-level and single-level to achieve a balance between performance and memory space. Our evaluation based on the Samsung Exynos 5250 SoC with real Android applications show that our system achieve 27% performance improvement compared with the baseline scheme. |
| Title | A Three-Stage-Write Scheme with Flip-Bit for PCM Main Memory |
| Author | Yanbin Li, *Xin Li, Lei Ju, Zhiping Jia (School of Computer Science and Technology, Shandong University, China) |
| Page | pp. 328 - 333 |
| Keyword | PCM, three-stage-write, two-stage-write, flip-N-write, performance improvement |
| Abstract | Phase-change memory (PCM) is a non-volatile memory which suffers slow write performance and limited write endurance. Besides, writing a one to a PCM cell needs longer time but less electrical current than writing a zero. In traditional PCM, zeros and ones in a word are written at the same time and word write time has to be the time to write a one, thus incurring time waste. In this paper, we propose a three-stage write scheme with flip-bit for PCM main memory to reduce the number of changed bits and write latency. In our scheme, write operation is divided into comparison, write-0 and write-1 stages. In the comparison stage, new data and old data are compared and the new data is re-encoded by a flip-bit to minimize changed bits. Then the flip-bit and re-encoded data are written to PCM cells in an accelerating manner. All zero bits and one bits are written separately in later two stages to avoid the time waste in traditional write. Our scheme shrinks time consumption and reduces bit changes caused by write operation over other existing schemes. The experimental results show that this scheme decreases 43.5% bit changes, 16.6% write time and 34.6% write energy consumption on average. |
| Slides |
| Title | A Garbage Collection Aware Stripping Method for Solid-State Drives |
| Author | *Min Huang (Harbin Institute of Technology, China), Yi Wang (Shenzhen University/Hong Kong Polytechnic University, China), Zhaoqing Liu, Liyan Qiao (Harbin Institute of Technology, China), Zili Shao (The Hong Kong Polytechnic University, Hong Kong) |
| Page | pp. 334 - 339 |
| Keyword | SSD, garbage collection, stripping, parallelism |
| Abstract | This paper presents a Garbage Collection Stripping Method (GCAS), which is the first work to the best of our knowledge that jointly optimizes garbage collection operation and the I/O performance of stripping methods in NAND flash memory based SSDs. We implemented GCAS on a real hardware platform. Experiments show that GCAS can achieve a reduction up to 15.87% for the number of the block erase count and avoid 47.6% worst cases response time compared with Round-Robin stripping method. |
| Title | Unified Non-Volatile Memory and NAND Flash Memory Architecture in Smartphones |
| Author | *Renhai Chen (The Hong Kong Polytechnic University, Hong Kong), Yi Wang (Shenzhen University, China), Jingtong Hu (Oklahoma State University, U.S.A.), Duo Liu (Chongqing University, China), Zili Shao (The Hong Kong Polytechnic University, Hong Kong), Yong Guan (Capital Normal University, China) |
| Page | pp. 340 - 345 |
| Keyword | Secondary Storage, Smartphones, Non-volatile Memory |
| Abstract | I/O is becoming one of major performance bottlenecks in NAND-flash-based smartphones. Novel NVMs can provide fast read/write operations. In this paper, we propose an unified NVM/flash architecture to improve the I/O performance. A cross-layer transparent scheme, vFlash (Virtualized Flash), is also proposed to manage the unified architecture. The experimental results show that the read and write performance for the proposed scheme is 2.45 times and 3.37 times better than that of the stock Android 4.2 system, respectively. |