| Title | A Retargetable and Accurate Methodology for Logic-IP-Internal Electromigration Assessment |
| Author | Palkesh Jain (Qualcomm India Pvt Ltd, India), *Sachin S. Sapatnekar (University of Minnesota, U.S.A.), Jordi Cortadella (Universitat Politècnica de Catalunya, Spain) |
| Page | pp. 346 - 351 |
| Keyword | Electromigration, Characterization, Library, Automotive, Reliability |
| Abstract | A new methodology for SoC-level logic-IP-internal EM verification is presented in this work, which provides an on-the-fly retargeting capability for reliability constraints. This flexibility is at design-verification stage, in the form of allowing arbitrary specifications (of lifetimes, temperatures, voltages and failure rates), as well as interoperability of IPs across foundries. The methodology is characterization and reuse based, and naturally incorporates complex effects like clock gating and variable switching rates at different pins. The benefit from such a framework is demonstrated on a 28nm design, with close SPICE-correlation and verification in a retargeted reliability condition. |
| Title | New Electromigration Modeling and Analysis Considering Time-Varying Temperature and Current Densities |
| Author | Hai-Bao Chen, *Sheldon X.-D. Tan, Xin Huang (Department of Electrical Engineering, University of California, Riverside, U.S.A.), Valeriy Sukharev (Mentor Graphics Corporation, U.S.A.) |
| Page | pp. 352 - 357 |
| Keyword | Electromigration, Reliability, Temperature, Current density |
| Abstract | Electromigration (EM) is projected to be the major reliability issue for current and future VLSI technologies. However, existing EM models and assessment techniques are mainly based on the constant current density and temperature. Such models will not work well at the system level as the current density (power) and temperature are changing with time due to different tasks (their loans) applied at run time. Existing EM approaches using average current density or temperature, however, will lead to significant errors as shown in this work. In this paper, we propose a new physics-based EM model considering time-varying temperature and current density, which reflects a more practical chip working conditions especially for multi-core and emerging 3D ICs. We study the impacts of the time-varying current densities and temperature profiles on EM-induced lifetime of a wire for both nucleation phase and growth phase. We propose a fast stress calculation method for given time-varying temperature and current densities for the nucleation phase. We further develop new formulae to compute the resistance changes in growth phase due to changing temperature and current densities. Experimental results show that the proposed method shows an excellent agreement with the detailed numerical analysis but with much improved efficiency. |
| Title | Generating Circuit Current Constraints to Guarantee Power Grid Safety |
| Author | *Zahi Moudallal, Farid N Najm (University of Toronto, Canada) |
| Page | pp. 358 - 365 |
| Keyword | Integrated Circuits, Power Grid, Verification, Generating Constraints |
| Abstract | Efficient and early verification of the chip power distribution network is a critical step in modern IC design. Vectorless verification, developed over the last decade as an alternative to simulation based methods, requires user-specified current constraints and checks if the corresponding worst-case voltage drops at all grid nodes are below user-specified thresholds. However, obtaining/specifying the current constraints remains a burdensome task for design teams. In this paper, we define and address the inverse problem: for a given grid, we will generate circuit current constraints which, if adhered to by the underlying logic, would guarantee grid safety. There are many potential applications for this approach, including various grid quality metrics, as well as power grid-aware placement and floorplanning. We give a rigorous problem definition and develop some key theoretical results related to maximality of the current space defined by the constraints. Based on this, we then develop two algorithms for constraints generation that target key quality metrics like the peak total power allowed by the grid and the uniformity of the temperature distribution. |
| Slides | |
| Title | BEE: Predicting Realistic Worst Case and Stochastic Eye Diagrams by Accounting for Correlated Bitstreams and Coding Strategies |
| Author | Aadithya Karthik (UC Berkeley, U.S.A.), Sayak Ray (Princeton University, U.S.A.), *Jaijeet Roychowdhury (UC Berkeley, U.S.A.) |
| Page | pp. 366 - 371 |
| Keyword | Worst case eye diagram, Peak distortion analysis, Coding/Communications Schemes, Inter-Symbol Interference, Jitter |
| Abstract | Modern high-speed links and I/O subsystems often employ sophisticated coding strategies to boost error resilience. The analysis of such systems, which involves accurate prediction of worst-case and stochastic eye diagrams, is challenging. Existing techniques such as Peak Distortion Analysis (PDA) typically predict overly pessimistic eye diagrams. Monte-Carlo methods, on the other hand, often predict overly optimistic eye diagrams, and they are also very time-consuming. As an alternative, we present BEE, an accurate and efficient computational technique to predict realistic worst-case and stochastic eye diagrams in modern high-speed links with neither excessive pessimism nor undue optimism. BEE is able to fully and correctly take into account many features underlying modern communications systems, including arbitrary transmit-side coding schemes as well as non-idealities such as ISI, crosstalk, asymmetric rise/fall times, jitter, parameter variability, etc. We demonstrate BEE on links involving (7,4)-Hamming and 8b/10b SERDES encoders, featuring channels that give rise to multiple reflections, dispersion, loss, and overshoot/undershoot. BEE successfully predicts actual worst case eye openings in all these real-world systems, which can be twice as large as the eye openings predicted by overly pessimistic methods like PDA. Also, BEE can be an order of magnitude faster than Monte-Carlo based eye estimation methods. |
| Title | A Fast Parallel Approach for Common Path Pessimism Removal |
| Author | *Chung-Hao Tsai, Wai-Kei Mak (National Tsing Hua University, Taiwan) |
| Page | pp. 372 - 377 |
| Keyword | Timing analysis, Common path pessimism removal |
| Abstract | Static timing analysis has always been indispensable in integrated circuit design. In order to consider design and electrical complexities (e.g., crosstalk coupling, voltage drops) as well as manufacturing and environmental variations, timing analysis is typically done using an “early-late” split. The early-late split timing analysis enables timers to effectively account for any within-chip variation effects. However, this dual-mode analysis may introduce unnecessary pessimism, which can lead to an over-conservative design. Thus, common path pessimism removal (CPPR) is introduced to eliminate this pessimism during timing analysis. A naive approach would require the analysis of all paths in the design. For today’s designs with millions of gates, enumerating all paths is impractical. In this paper, we propose a new approach to effectively prune the redundant paths and develop a multi-threaded timing analysis tool called MTimer for fast and accurate CPPR. The results show that our timer can achieve 3.53X speedup comparing with the winner of the TAU 2014 contest and maintain 100% accuracy on removing common path pessimism during timing analysis. |