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The 20th Asia and South Pacific Design Automation Conference

Session 5C  Next-Generation Clock Network Synthesis
Time: 13:50 - 15:30 Wednesday, January 21, 2015
Location: Room 105
Chairs: Atsushi Takahashi (Tokyo Inst. of Tech.), David Z. Pan (Univ. of Texas, Austin, U.S.A.)

5C-1 (Time: 13:50 - 14:15)
TitleUseful Clock Skew Scheduling Using Adjustable Delay Buffers in Multi-Power Mode Designs
Author*Juyeon Kim, Taewhan Kim (Seoul National Univ., Republic of Korea)
Pagepp. 466 - 471
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5C-2 (Time: 14:15 - 14:40)
TitleFast Clock Skew Scheduling Based on Sparse-Graph Algorithms
Author*Rickard Ewetz (Purdue Univ., U.S.A.), Shankarshana Janarthanan (NVIDIA, U.S.A.), Cheng-Kok Koh (Purdue Univ., U.S.A.)
Pagepp. 472 - 477
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5C-3 (Time: 14:40 - 15:05)
TitleModeling and Optimization of Low Power Resonant Clock Mesh
Author*Wulong Liu (Tsinghua Univ., China), Guoqing Chen (Research Lab, Advanced Micro Devices, China), Yu Wang, Huazhong Yang (Tsinghua Univ., China)
Pagepp. 478 - 483
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5C-4 (Time: 15:05 - 15:30)
TitleSynthesis of Resonant Clock Networks Supporting Dynamic Voltage / Frequency Scaling
Author*Seyong Ahn, Minseok Kang (Seoul National Univ., Republic of Korea), Marios C. Papaefthymiou (Univ. of Michigan, U.S.A.), Taewhan Kim (Seoul National Univ., Republic of Korea)
Pagepp. 484 - 489
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