| Title | Fast Clock Skew Scheduling Based on Sparse-Graph Algorithms |
| Author | *Rickard Ewetz (Purdue University, U.S.A.), Shankarshana Janarthanan (NVIDIA corporation, U.S.A.), Cheng-Kok Koh (Purdue University, U.S.A.) |
| Page | pp. 472 - 477 |
| Keyword | Clock synthesis, skew, scheduling |
| Abstract | Incorporating timing constraints explicitly imposed
by the data and control paths during clock network synthesis can
enhance the robustness of the synthesized clock networks. With
these constraints, a clock scheduler can be used to guide the synthesis of a clock network by specifying a set of feasible arrival
times at the respective sequential elements. Clock scheduling can
be either static or dynamic. In static clock scheduling, a clock
schedule is first specified; next, a clock network is constructed
realizing the prescribed schedule. Clock trees constructed using
this approach may consume significant routing resources. In dynamic clock scheduling, the clock tree and clock schedule are both
simultaneously constructed and determined, respectively. In earlier studies, the scalability of dynamic clock scheduling, which is
essentially a shortest path problem, has been limited. The bottleneck is in finding the shortest paths between different vertices
in an incrementally changing weighted graph. In this work, we
present two clock schedulers that address the scalability issues by
exploiting the sparsity of this weighted graph. Experimental results show that the proposed clock schedulers are one to two orders of magnitude faster compared to a published scheduler in an
earlier work. The proposed clock schedulers are scalable, and are
tested on a synthesized circuit with 348 710 cells, 57 491 sequential elements, and 496 727 explicit timing constraints. |
| Slides |
| Title | Modeling and Optimization of Low Power Resonant Clock Mesh |
| Author | *Wulong Liu (Tsinghua University, China), Guoqing Chen (Research Lab, Advanced Micro Devices, China), Yu Wang, Huazhong Yang (Tsinghua University, China) |
| Page | pp. 478 - 483 |
| Keyword | Resonant clock, Clock mesh, Low Power, Transmission line |
| Abstract | Power consumption is becoming more critical in modern IC designs and clock network is one of the major contributors for on-chip power. Resonant clock has been investigated as a potential solution to reduce the power consumption in clock network by recycling the energy with on-chip inductors. Most of the previous resonant clock work focuses on H-tree structures, while in this work, we propose a modeling and optimization method for the resonant clock mesh structure, which suffers from the high power consumption much more than the tree structure. Closed-form expressions for the transfer function, skew, and power are derived. Based on these expressions, the buffer size, LC tank location, grid size, wire width, and the sparsity of buffers and LC tanks are fully explored to make trade-offs among power, skew, and area. The exploration is also extended to 3D ICs and different mesh structures are evaluated. |
| Slides |
| Title | Synthesis of Resonant Clock Networks Supporting Dynamic Voltage / Frequency Scaling |
| Author | *Seyong Ahn, Minseok Kang (Seoul National University, Republic of Korea), Marios C. Papaefthymiou (University of Michigan, U.S.A.), Taewhan Kim (Seoul National University, Republic of Korea) |
| Page | pp. 484 - 489 |
| Keyword | resonant clock, synthesis, low power |
| Abstract | So far no works have addressed the problem of synthesizing resonant clock networks that are able to operate under the designs with DVFS capability even though the problem is potentially very important to maximize the synergy effect on saving power. In this context, this work proposes a comprehensive solution to the problem. Precisely, we propose a two-phase synthesis algorithm: (1) formulating the problem of inductor allocation, placement, and adjustable-sizing to support DVFS into a weighted set cover problem with the objective of minimizing total area of inductors followed by (2) performing the task of resizing adjustable driving buffers to support the switch of driving strength according to the clock frequencies by DVFS. |
| Slides |