| Title | Enhanced LCCG: A Novel Test Clock Generation Scheme for Faster-than-at-Speed Delay Testing |
| Author | *Songwei Pei, Ye Geng (Department of Computer Science and Technology, Beijing University of Chemical Technology, China), Huawei Li (Key Laboratory of Computer System and Architecture, Institute of Computing Technology, China), Jun Liu (School of Computer and Information, Hefei University of Technology, China), Song Jin (School of Electrical and Electronic Engineering,North China Electric Power University, China) |
| Page | pp. 514 - 519 |
| Keyword | faster-than-at-speed, delay testing, small delay defects |
| Abstract | On-chip faster-than-at-speed delay testing provides a promising way for small delay defect detection. However, the frequency of on-chip generated test clock would be impacted by process variations. Hence, it requires determining the actual frequency of generated test clock to ensure the effectiveness of faster-than-at-speed delay testing. In this paper, we present a novel test clock generation scheme, namely Enhanced LCCG, for faster-than-at-speed delay testing. In the proposed scheme, faster-than-at-speed test clock is firstly generated by configuring the corresponding control information specified in the test pattern into Enhanced LCCG. Then, by constructing oscillation paths and counting the corresponding oscillation iteration numbers, the actual frequency of test clock can be measured and calculated with high resolution. Experimental results are presented to validate the proposed method. |
| Title | An Efficient 3D-IC On-Chip Test Framework to Embed TSV Testing in Memory BIST |
| Author | Liang-Che Li, Wen-Hsuan Hsu, *Kuen-Jong Lee (National Cheng Kung University, Taiwan), Chun-Lung Hsu (Industrial Technology Research Institute, Taiwan) |
| Page | pp. 520 - 525 |
| Keyword | 3D-IC, TSV testing, Memory testing |
| Abstract | 3D-ICs use Through Silicon Via (TSV) to reduce the connection length and enhance I/O bandwidth. In this paper, we present an efficient on-chip 3D-ICs testing framework to merge TSV and BIST-based memory testing. During the memory testing, memory test patterns are also used to test TSVs. And we can perform TSV testing for many times during memory test time to improve detectability of TSVs. The experimental results will show the test time saving and the low area costing. |
| Title | An Integrated Temperature-Cycling Acceleration and Test Technique for 3D Stacked ICs |
| Author | *Nima Aghaee, Zebo Peng, Petru Eles (Linköping University, Sweden) |
| Page | pp. 526 - 531 |
| Keyword | 3D Stacked IC test, temperature cycling, test scheduling, early-life failures |
| Abstract | Through silicon vias in 3D ICs are subject to undesirable early-life effects such as protrusion and voids. Operating the ICs under extreme temperature cycling can accelerate these early-life failures and make them detectable. An integrated temperature-cycling acceleration and test technique is introduced in this paper that combines a temperature-cycling acceleration procedure with pre-, mid-, and post-bond tests for 3D ICs. The proposed method schedules the tests, cooling intervals, and heating sequences in order to provide the required temperature cycling effect. |
| Slides |
| Title | Software-Based Test and Diagnosis of SoCs Using Embedded and Wide-I/O DRAM |
| Author | *Sergej Deutsch, Krishnendu Chakrabarty (Duke University, U.S.A.) |
| Page | pp. 532 - 537 |
| Keyword | Fault Diagnosis, Test-data Compression, Online Test |
| Abstract | We propose a test and diagnosis solution that makes use of software-based decompression of deterministic scan-test pattern and allows for test application from on-chip DRAM to the logic die, extending traditional hardware-based methods and allowing for online scan-based test and diagnosis. This solution therefore targets SoCs that contain, in addition to a microprocessor, multiple digital-logic cores and glue logic, all of which need to be tested using scan test patterns. |