| Title | Logic-DRAM Co-Design to Efficiently Repair Stacked DRAM With Unused Spares |
| Author | Minjie Lv, *Hongbin Sun, Jingmin Xin, Nanning Zheng (Institute of Artificial Intelligence and Robotics, Xi'an Jiaotong University, China) |
| Page | pp. 538 - 543 |
| Keyword | Memory repair, 3D IC, Design for repair, DRAM, logic-DRAM co-design |
| Abstract | This paper exploits a cost efficient approach to repair 3D integration induced defective cells in stacked DRAM with unused spares, by leveraging logic-DRAM co-design. In particular, we propose to make the DRAM array open its spares to off-chip access by small architecture modification, and further design the defective address comparison and redundant address remapping with very efficient architecture on logic die to achieve the equivalent memory repair. |
| Title | Electromigration-Aware Redundant via Insertion |
| Author | Jiwoo Pak, Bei Yu, *David Z. Pan (The University of Texas at Austin, U.S.A.) |
| Page | pp. 544 - 549 |
| Keyword | Electromigration, Via, Optimization |
| Abstract | As the feature size shrinks, electromigration (EM) becomes
a more critical reliability issue in IC design. EM around the
via structures accounts for much of the reliability problems
in ICs, and the insertion of redundant vias can mitigate the
adverse effect of EM by reducing current density. In this
paper, we model EM reliability of redundant via structures,
considering current distribution with different via layouts.
Based on our EM model, we choose redundant via layouts
that can increase the EM-related lifetime by using integer
linear programming (ILP). To overcome the runtime issue
of ILP, we also propose speed-up techniques for our EM-
aware redundant via insertion. Experimental results show
that our scheme brings much more EM-robustness to circuits
with the similar number of redundant vias, compared to the
conventional redundant via insertion techniques. |
| Title | Synthesis of Resilient Circuits from Guarded Atomic Actions |
| Author | Yuankai Chen (Synopsys Inc., U.S.A.), *Hai Zhou (Northwestern University, U.S.A.) |
| Page | pp. 550 - 555 |
| Keyword | Reliability, High-level synthesis |
| Abstract | With aggressive scaling of minimum feature sizes, supply voltages, and design guard-band, transient faults have become critical issues in modern electronic circuits. Synthesis from guarded atomic actions has been investigated by Arvind et al. to explore non-determinism for hardware concurrency. We show in this work that non-determinism in the guarded atomic actions can be further explored for synthesis of resilient circuits. When an error happens in one atomic action, it may not need to be recomputed if there exist other feasible actions. Such flexibilities will be increased in the specification and explored in the synthesis for efficient error resiliency. This expanded solution space offers the possibility of performance optimization. Experimental results demonstrate the effectiveness and efficiency of our synthesis approach. |
| Title | Incremental Latin Hypercube Sampling for Lifetime Stochastic Behavioral Modeling of Analog Circuits |
| Author | Yen-Lung Chen (National Central University, Taiwan), Wei Wu (University of California, Los Angeles, U.S.A.), *Chien-Nan Jimmy Liu (National Central University, Taiwan), Lei He (University of California, Los Angeles, U.S.A.) |
| Page | pp. 556 - 561 |
| Keyword | Stochastic Behavioral Modeling, Lifetime yield, Incremental sampling, Analog, Aging effects |
| Abstract | In advanced technology node, not only process variations but also aging effects have critical impacts on circuit performance. Most of existing works consider process variations and aging effects separately while building the corresponding behavior models. Because of the time-varied circuit property, parametric yield need to be reanalyzed in each aging time step. This results in expensive simulation cost for reliability analysis due to the huge number of circuit simulation runs. In this paper, an incremental Latin hypercube sampling (LHS) approach is proposed to build the stochastic behavior models for analog/mixed-signal (AMS) circuits while simultaneously considering process variations and aging effects. By reusing previous sampling information, only a few new samples are incrementally updated to build an accurate stochastic model in different time steps, which significantly reduces the number of simulations for aging analysis. Experiments on an operational amplifier and a DAC circuit achieve 242x speedup over traditional reliability analysis method with similar accuracies. |
| Slides |