| Title | (Invited Paper) Toward Large-Scale Access-Transistor-Free Memristive Crossbars |
| Author | Amirali Ghofrani, Miguel Angel Lastras-Montaño, *K.-T. Tim Cheng (University of California at Santa Barbara, U.S.A.) |
| Page | pp. 563 - 568 |
| Keyword | ReRAM, access-transistor-free crossbar, write disturbance, sneak current, leakage current |
| Abstract | Memristive crossbars have been shown to be excellent candidates for building an ultra-dense memory system because a per-cell access-transistor may no longer be necessary. However, the elimination of the access-transistor introduces several parasitic effects due to the existence of partially-selected devices during memory accesses, which could limit the scalability of access-transistor-free (ATF) memristive crossbars. In this paper we discuss these challenges in detail and describe some solutions addressing these challenges at multiple levels of design abstraction. |
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| Title | (Invited Paper) Read Circuits for Resistive Memory (ReRAM) and Memristor-Based Nonvolatile Logics |
| Author | *Meng-Fan Chang, Albert Lee, Chien-Chen Lin (National Tsing Hua University, Taiwan), Mon-Shu Ho (National Chung Hsin University, Taiwan), Ping-Cheng Chen (I-Shou University, Taiwan), Chia-Chen Kuo, Ming-Pin Chen, Pei-Ling Tseng, Tzu-Kun Ku (Industrial Technology Research Institute, Taiwan), Chien-Fu Chen, Kai-Shin Li, Jia-Min Shieh (National Nano Device Laboratories, Taiwan) |
| Page | pp. 569 - 574 |
| Keyword | ReRAM, Memristor, sense amplifier |
| Abstract | Resistive memory device (Memristor) is one of the candidates for energy-efficient nonvolatile memory and nonvolatile logics (nvLogics) in the applications of wearable, IoT, cloud computing, and big-data processing. However, resistive RAM (ReRAM) and memristor-based nvLogics suffer limited perfroamnce and low yield due to process variations in transistors and resistance of memristor. This presentation discusses the design challenges in read circuits for high-speed, area-efficient, and low-voltage ReRAM and nvLogics. Memristor-based nvLogics, such nonvolatile-SRAM (nvSRAM), nonvolatile flip-flops (nvFF), and nonvolatile TCAM (nvTCAM) are included in this presentation. Several silicon-verified solutions on read scheme and sense amplifiers are also discussed in this presentation. |
| Title | (Invited Paper) 3D ReRAM with Field Assisted Super-Linear Threshold (FASTTM) Selector Technology for Super-Dense, Low Power, Low Latency Data Storage Systems |
| Author | Sung Hyun Jo, Tanmay Kumar, Mehdi Asnaashari, Wei D. Lu, *Hagop Nazarian (Crossbar Inc., U.S.A.) |
| Page | p. 575 |
| Abstract | 3D Resistive Ram (ReRAM) technology exhibits the best attributes to suite present and emerging non-volatile memory storage applications. However, the major challenge to make ReRAM work in a 3D crossbar array is the integration of a selector device with an ReRAM device. The selector device will solve the so called “sneak path” barrier and enable large density memory arrays with low power consumption. Here we report a Field Assisted Superlinear Threshold (FAST) Selector technology that overcomes the sneak path barrier with a selectivity ratio of 10e10. The switching and recover speed, on/off ratio, switching slope, W/E and read endurance, and variability of the FAST selector will be discussed. Prototype 1S1R devices with the FAST selector integrated with a low current ReRAM cell have been demonstrated and characterized.
This technology readily leads to the implementation of 1TnR and 3D ReRAM architectures, and provides significant architectural benefits, power reduction, performance improvement, and overall system cost reduction advantages for IoT, enterprise storage, mobile, and wearable systems utilizing ReRAM technology. |
| Title | (Invited Paper) Modeling and Design Optimization of ReRAM |
| Author | *J. F. Kang, H. T. Li, P. Huang, Z. Chen, B. Gao, X. Y. Liu (Peking University, China), Z. Z. Jiang, H.-S. P. Wong (Stanford University, U.S.A.) |
| Page | pp. 576 - 581 |
| Keyword | emerging memory, resistive switching memory, SPICE model |
| Abstract | Resistive switching devices (RRAM) have been widely studied for the application in the next-generation data storage and neurormorphic computing systems. To meet the requirements of device-circuit-system co-design and optimization, A SPICE model of RRAM that can reproduce the device characteristics in circuit simulations is needed. In this talk, we will address a developed physical based SPICE model that can capture all the essential features of HfOx-based RRAM including the DC/AC and multi-level switching behaviors, switching reliability (endurance and read disturb) and variation characteristics, and resistance distributions. A novel extraction strategy is developed to extract the critical model parameters from the fabricated RRAM devices. A variety of electrical measurements on various RRAMs are performed to verify and calibrate the model. The verified model can be applied to explore a wide range of applications including: 1) variation-aware and reliability-emphasized system design; 2) system performance evaluation; 3) array architecture optimization. This verified design tool not only enables the system design but also provides solutions for the system optimization that capitalize on device/circuit interaction for both data storage and neuromorphic computing applications. |
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