| Title | Compact Modeling of Microbatteries Using Behavioral Linearization and Model-Order Reduction |
| Author | Mohammed Shemsu Nesro (Masdar Institute of Technology, United Arab Emirates), Lizhong Sun (Applied Materials, U.S.A.), *Ibrahim (Abe) M. Elfadel (Masdar Institute of Science and Technology, United Arab Emirates) |
| Page | pp. 713 - 718 |
| Keyword | compact modeling, micro batteries, model-order reduction |
| Abstract | Thin-film, solid-state microbatteries represent now a viable alternative for powering small form-factor microsystems or storing the power harvested by energy microsensors. One obstacle to their widespread use in integrated systems has been the absence of a high-fidelity, physics-based, compact model describing their operation and enabling their design and verification in the same CAD environment as integrated systems or energy harvesters. In this work, we develop and validate such a model using a thorough analysis of the electrochemistry of a thin-film, solid-state lithium-ion microbattery. Our compact model is based on carefully validating and exploiting the electroneutrality assumption of the thin-film, solid-state electrolyte. Such an assumption enables the replacement of the nonlinear partial differential equations (PDEs) describing the microbattery electrochemistry with linear ones without virtually any loss in accuracy. We apply to the latter equations the well-established methodology of Arnoldi-based model order reduction (MOR) techniques to develop a compact microbattery model capable of reproducing its input-output electrical behavior with less than 1% error with respect to the full nonlinear PDEs and of at least 30X speed up in transient simulation. |
| Title | GPU-Accelerated Parallel Monte Carlo Analysis of Analog Circuits by Hierarchical Graph-Based Solver |
| Author | Yan Zhu, *Sheldon X.-D. Tan (University of California, Riverside, U.S.A.) |
| Page | pp. 719 - 724 |
| Keyword | hierarchical graph based solver, Monte Carlo Analysis, symbolic method, GPU |
| Abstract | In this article, we propose a new parallel matrix solver, which is very amenable for Graphic Process Unit (GPU) based fine-grain massively-threaded parallel computing. The new method is based on the graph-based symbolic analysis technique to generate the computing sequence of determinants in terms of determinant decision diagrams (DDDs). DDD represents very simple data dependence and data parallelism, which can be explored much easier by GPU massively-threaded parallel computing than existing LU-based methods. The new method is based on the hierarchical determinant decision diagrams (HDDDs). Inspired by the inherent data parallelism and simple data dependence in the evaluation process of HDDD, we design GPU-amenable continuous data structures to enable fast memory access and evaluation of massive parallel threads. In addition to parallelism in DDD graph, the new algorithm can naturally explore data independence existing in Monte Carlo and frequency domain analysis. The resulting algorithm is a generalpurpose matrix solver suitable for fine-grain massive GPU-based computing for any circuit matrices. Experimental results show that the new evaluation algorithm can achieve about two orders of magnitude speedup over the serial CPU based evaluation and more than 4X speedup over numerical SPICE-based simulation method on some large analog circuits. |
| Title | Automated Generation of Hybrid System Models for Reachability Analysis of Nonlinear Analog Circuits |
| Author | *Hyun-Sek Lukas Lee (Institute of Microelectronic Systems, Leibniz Universität Hannover, Germany), Matthias Althoff (Institute of Robotics and Embedded Systems, Technische Universität München, Germany), Stefan Hoelldampf, Markus Olbrich, Erich Barke (Institute of Microelectronic Systems, Leibniz Universität Hannover, Germany) |
| Page | pp. 725 - 730 |
| Keyword | formal verification, reachability analysis, hybrid model, piecewise-linear, state-space explosion problem |
| Abstract | We address the problem of formally verifying analog circuits with an uncertain initial set by computing their reachable set. Our method is based on linearizations of the nonlinear circuit, which results in a piecewiselinear system. To limit the number of required locations, our approach computes locations on-the-fly. The method is fully automatic and only requires a circuit netlist. It provides a guaranteed bound on the number of linearization locations that have to be explicitly computed for such a circuit. |
| Title | Area Efficient Device-Parameter Estimation Using Sensitivity-Configurable Ring Oscillator |
| Author | *Shoichi Iizuka, Yuma Higuchi, Masanori Hashimoto, Takao Onoye (Osaka University, Japan) |
| Page | pp. 731 - 736 |
| Keyword | device-parameter estimation, ring oscillator, manufacturing variability, variation sensor |
| Abstract | This paper proposes an area efficient device-parameter estimation method with sensitivity-configurable ring oscillator (RO).
This sensitivity-configurable RO has a number of configurations and the proposed method exploits this property for reducing sensor area and/or improving estimation accuracy.
Experimental results with a 32nm predictive technology model show that the proposed method can reduce the estimation error by 49% or reduce the sensor area by 75% while keeping the accuracy. |
| Slides |