| Title | On Test Syndrome Merging for Reasoning-Based Board-Level Functional Fault Diagnosis |
| Author | Zelong Sun (The Chinese University of Hong Kong, Hong Kong), *Li Jiang (Shanghai Jiao Tong University, China), Qiang Xu (The Chinese University of Hong Kong, Hong Kong), Zhaobo Zhang, Zhiyuan Wang, Xinli Gu (Huawei Technologies, Inc., U.S.A.) |
| Page | pp. 737 - 742 |
| Keyword | Board Test, Diagnosis |
| Abstract | Machine learning algorithms are advocated for automated di agnosis of board-level functional failures due to the extreme complexity of the problem. Such reasoning-based solutions, however, remain ineffective at the early stage of the product cycle, simply because there are insufficient historical data for training the diagnostic system that has a large number of test syndromes. In this paper, we present a novel test syndrome merging methodology to tackle this problem. That is, by lever aging the domain knowledge of the diagnostic tests and the board structural information, we adaptively reduce the feature size of the diagnostic system by selectively merging test syn- dromes such that it can effectively utilize the available training cases. Experimental results demonstrate the effectiveness of the proposed solution. |
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| Title | Event-Driven Transient Error Propagation: A Scalable and Accurate Soft Error Rate Estimation Approach |
| Author | Mojtaba Ebrahimi, Razi Seyyedi, Liang Chen, *Mehdi Tahoori (Karlsruhe Institute of Technology, Germany) |
| Page | pp. 743 - 748 |
| Keyword | Soft errors, Relibility, fault simulation |
| Abstract | Fast and accurate soft error vulnerability assessment is an integral part of cost-effective robust system design. The de facto approach is expensive fault simulation or emulation in which the error is injected in random bits and cycles, and then the effect is simulated for millions of cycles. In this paper, we propose a novel alternative approach to obtain the soft error vulnerability by integrating transient error propagation in an event-driven gate-level logic simulator which captures the combined effect of various masking factors. By carefully combining various generated errors at different cycles, in one pass all the error generation and propagation effects across all bits and all cycles are analyzed. This enables us to drastically reduce the runtime while maintaining the accuracy compared to statistical fault injection. |
| Title | A Novel Methodology for Testing Hardware Security and Trust Exploiting On-Chip Power Noise Measurement |
| Author | *Daisuke Fujimoto, Makoto Nagata (Kobe University, Japan), Shivam Bhasin, Jean-Luc Danger (Telecom Paristech, France) |
| Page | pp. 749 - 754 |
| Keyword | Test, Hardware Security, Trust, Side-channel measurement, Trojan Detection |
| Abstract | For security-critical applications, the security and trust of devices must be tested before shipping. In this paper, we promote the use of On-Chip Power noise Measurements (OCM), in order to test security using side-channel techniques. We then propose for the first time a standard side-channel measurement setup using OCM. Finally, we provide some key ideas on methodology to integrate the validation of hardware security and trust in the standard testing flow, exploiting OCM. |
| Title | Hardware Trojan Detection Using Exhaustive Testing of k-bit Subspaces |
| Author | Nicole Lesperance, Shrikant Kulkarni, *Kwang-Ting Cheng (UC Santa Barbara, U.S.A.) |
| Page | pp. 755 - 760 |
| Keyword | Hardware Trojan, Hardware Security, Cryptographic Hardware, Pseudoexhaustive Testing |
| Abstract | Post-silicon hardware Trojan detection is challenging because the attacker only needs to implement one of many possible design modifications, while the verification effort must guarantee the absence of all imaginable malicious circuitry. Existing test generation strategies for Trojan detection use controllability and observability metrics to limit the modifications targeted. However, for cryptographic hardware, the n plaintext bits are ideal for an attacker to use in Trojan triggering because the size of n prohibits exhaustive testing, and all n bits have identical controllability, making it impossible to bias testing using existing methods. Our detection method addresses this difficult case by observing that an attacker can realistically only afford to use a small subset, k, of all n possible signals for triggering. By aiming to exhaustively cover all possible k subsets of signals, we guarantee detection of Trojans using less than k plaintext bits in the trigger. We provide suggestions on how to determine k, and validate our approach using an AES design. |
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