| Title | (Invited Paper) Heterogeneous Architecture Design with Emerging 3D and Non-Volatile Memory Technologies |
| Author | Qiaosha Zou, Matthew Poremba (Pennsylvania State Univ., U.S.A.), Rui He, Wei Yang, Junfeng Zhao (Huawei Shannon Lab, China), *Yuan Xie (Univ. of California, Santa Barbara, U.S.A.) |
| Page | pp. 785 - 790 |
| Detailed information (abstract, keywords, etc) | |
| Title | (Invited Paper) Alleviate Chip I/O Pin Constraints for Multicore Processors through Optical Interconnects |
| Author | *Zhehui Wang, Jiang Xu, Peng Yang, Xuan Wang, Zhe Wang, Luan H.K. Duong, Zhifei Wang, Haoran Li, Rafael K.V. Maeda, Xiaowen Wu (Hong Kong Univ. of Science and Tech., Hong Kong), Yaoyao Ye, Qinfen Hao (Huawei Technologies, China) |
| Page | pp. 791 - 796 |
| Detailed information (abstract, keywords, etc) | |
| Slides | |
| Title | (Invited Paper) A Fast and Accurate Network-on-Chip Timing Simulator with a Flit Propagation Model |
| Author | Ting-Shuo Hsu, Jun-Lin Chiu, Chao-Kai Yu, *Jing-Jia Liou (National Tsing Hua Univ., Taiwan) |
| Page | pp. 797 - 802 |
| Detailed information (abstract, keywords, etc) | |
| Slides | |
| Title | (Invited Paper) Application-Level Embedded Communication Tracer for Many-Core Systems |
| Author | *Chih-Tsun Huang, Kuan-Chun Tasi, Jun-Shen Lin, Hsiao-Wei Chien (National Tsing Hua Univ., Taiwan) |
| Page | pp. 803 - 808 |
| Detailed information (abstract, keywords, etc) | |