| Title | Timing-Based Anomaly Detection in Embedded Systems |
| Author | Sixing Lu, Minjun Seo, *Roman Lysecky (University of Arizona, U.S.A.) |
| Page | pp. 809 - 814 |
| Keyword | Non-intrusive monitoring, anomaly detection, mimicry attack |
| Abstract | Recent research has demonstrated that many systems are vulnerable to numerous types of malicious activity. As the pervasiveness of embedded systems with network connectivity continues to increase, embedded systems security has become a critical challenge. However, most existing techniques for detecting malware utilize software-based methods that incur significant performance overheads that are often not feasible in embedded systems. In this paper, we present an overview of a novel method for non-intrusively detecting malware in embedded system. The proposed technique utilizes timing requirements to improve detection performance and provide increased resilience to mimicry attacks. |
| Slides | |
| Title | Satisfiability Don't Care Condition Based Circuit Fingerprinting Techniques |
| Author | *Carson J Dunbar, Gang Qu (University of Maryland, U.S.A.) |
| Page | pp. 815 - 820 |
| Keyword | SDC, fingerprint, IP, SoC |
| Abstract | Circuit fingerprints allow the authors of design intellectual properties (IPs) to trace each copy of their IPs by embedding features, known as digital fingerprints, which are unique to each device. In this paper, we propose a novel gate replacement approach to encode fingerprints based on the inherent Satisfiability Don’t Care (SDC) conditions in the circuit. Moreover, existing fingerprinting schemes all require redesign of the circuit which makes it prohibitively expensive for manufacturing. We develop a practical method to implement our SDC-based circuit fingerprint. First, we introduce flexibilities during the logic synthesis phase by replacing certain library cells with versatile multiplexers (MUXs). The MUX can be configured either as the original gate or one of its replacements with identical functionality except the SDC conditions. Then at the post-silicon stage, we configure these MUXs to create distinct fingerprints. We consider standard benchmark circuits and demonstrate that even on these circuits with limited size, we can find sufficient locations to embed fingerprints. Simulation with TSMC 0.35μm technology shows non-trivial design overhead, however, such overhead will become negligible for large real-life circuits. |
| Slides | |
| Title | IC Piracy Prevention via Design Withholding and Entanglement |
| Author | Soroush Khaleghi, Kai Da Zhao, *Wenjing Rao (University of Illinois at Chicago, U.S.A.) |
| Page | pp. 821 - 826 |
| Keyword | Hardware Security, IC Piracy, Reverse Engineering, Design Withholding |
| Abstract | Globalization of the semiconductor industry has raised serious concerns about trustworthy hardware. Particularly, an untrusted manufacturer can steal the information of a design (Reverse Engineering), and/or produce extra chips illegally (IC Piracy). Among many candidates that address these attacks, Design Withholding techniques work by replacing a part of the design with a reconfigurable block on chip, so that none of the manufactured chips will function properly until they are activated in a trusted facility, where the withheld function is restored back into the reconfigurable block on chip. However, most existing approaches are ad-hoc based, and are facing two major challenges: 1) susceptibility to a category of algorithmic attacks, from attackers in a strong position, such as a manufacturer; and 2) scaling up the defense level is checkmated by the explosion of hardware cost that has to be paid at the designer’s side. In this paper, we propose a novel protection scheme, called Entanglement, which can substantially strengthen the Design Withholding framework: 1) the algorithmic attacks are prevented by forcing the attacker to solve a huge number of problems of high computational complexity; 2) the attack cost (in terms of computational complexity) is quantitatively controllable at the designer’s end, with low hardware overhead: while the cost of attack can be increased exponentially, the hardware overhead imposed on the designer’s side grows only linearly. The proposed work distinguishes itself from the previous works by not relying on the difficulty of finding the solution for some NP-Complete/NP-Hard problems, but rather, on the exponentially boosted number of such problems that an attacker has to solve, while carefully maintaining the growth of the hardware overhead to be scalable via Entanglement. |
| Slides | |
| Title | Vulnerability Analysis for Crypto Devices against Probing Attack |
| Author | *Lingxiao Wei, Jie Zhang, Feng Yuan, Yannan Liu (The Chinese University of Hong Kong, Hong Kong), Junfeng Fan (Open Security Research, China), Qiang Xu (The Chinese University of Hong Kong, Hong Kong) |
| Page | pp. 827 - 832 |
| Keyword | Probing Attack, Vulnerability Analysis, Crypto Devices |
| Abstract | Probing attack is a severe threat for the security of hardware cryptographic modules (HCMs). In this paper, we make the first step to evaluate the vulnerability of HCMs against probing attack, wherein we investigate the probing complexity and the key candidate reduction capability for probing attack on every signal in the circuit. We also present approximate solutions for the calculation of the proposed metrics to reduce computational complexity. Experimental results demonstrate that the proposed evaluation metric is both effective and efficient. |