| Author | Panelists: Hironori Ando (Synopsys, Japan), Kevin Yee (Cadence, U.S.A.), Randy Smith (Sonics, U.S.A.), Neil Parris (ARM, U.K.) |
| Abstract | Recent SoC uses a lot of IP’s. This session discuss what innovation will happen in the next generation of SoC design with IP’s and IP design itself. Four major IP vendors are invited and will talk their views for future design innovation of SoC with their IP’s which include numbers and types of IP’s such as digital, analog, RF and even a MEMS, variety such as CPU, GPU, memory, bus, interface and so on, usage models in design hierarchy and its modeling and integration methods of those IP’s. And also in order to achieve the SoC design innovation they will mention IP itself design methodology including planning, specification, implementation, verification, validation and qualification. Comments, questions and discussions with audiences at the panel are welcome. |