Tuesday, January 20, 2015 |
Room 103 | Room 102 | Room 104 | Room 105 |
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Opening & Keynote I 8:30 - 9:50 |
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10:20 - 12:10 |
10:20 - 12:00 |
10:20 - 12:00 |
10:20 - 12:00 |
13:50 - 15:30 |
13:50 - 15:30 |
13:50 - 15:30 |
13:50 - 15:30 |
15:50 - 17:30 |
15:50 - 16:40 |
15:50 - 17:30 |
15:50 - 17:30 |
Wednesday, January 21, 2015 |
Room 103 | Room 102 | Room 104 | Room 105 |
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Keynote II 9:00 - 9:50 |
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10:15 - 12:20 |
10:15 - 12:20 |
10:15 - 12:20 |
10:15 - 12:20 |
13:50 - 15:30 |
13:50 - 15:30 |
13:50 - 15:30 |
13:50 - 15:30 |
15:50 - 17:30 |
15:50 - 17:30 |
15:50 - 17:30 |
15:50 - 17:30 |
18:00 - 20:00 |
Thursday, January 22, 2015 |
Room 103 | Room 102 | Room 104 | Room 105 |
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Keynote III 9:00 - 9:50 |
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10:15 - 12:20 |
10:15 - 12:20 |
10:15 - 12:20 |
10:15 - 12:20 |
13:50 - 15:30 |
13:50 - 15:30 |
13:50 - 15:30 |
13:50 - 15:30 |
15:50 - 17:30 |
15:50 - 17:30 |
15:50 - 17:30 |
15:50 - 17:30 |
Tuesday, January 20, 2015 |
Title | (Keynote Address) The Required Technologies for Automotive towards 2020 |
Author | *Udo Wolz (Bosch, Japan) |
Page | p. 1 |
Detailed information (abstract, keywords, etc) |
Title | An HDL-Synthesized Gated-Edge-Injection PLL with A Current Output DAC |
Author | *Dongsheng Yang, Wei Deng, Tomohiro Ueno, Teerachot Siriburanon, Satoshi Kondo, Kenichi Okada, Akira Matsuzawa (Tokyo Inst. of Tech., Japan) |
Page | pp. 2 - 3 |
Detailed information (abstract, keywords, etc) | |
Slides |
Title | An Oscillator-Based True Random Number Generator with Process and Temperature Tolerance |
Author | Takehiko Amaki, *Masanori Hashimoto, Takao Onoye (Osaka Univ., Japan) |
Page | pp. 4 - 5 |
Detailed information (abstract, keywords, etc) | |
Slides |
Title | Implementation of Double Arbiter PUF and Its Performance Evaluation on FPGA |
Author | *Takanori Machida (Univ. of Electro-Communications, Japan), Dai Yamamoto (Fujitsu Labs., Japan), Mitsugu Iwamoto, Kazuo Sakiyama (Univ. of Electro-Communications, Japan) |
Page | pp. 6 - 7 |
Detailed information (abstract, keywords, etc) |
Title | A Negative-Resistance Sense Amplifier for Low-Voltage Operating STT-MRAM |
Author | *Yohei Umeki, Koji Yanagida (Kobe Univ., Japan), Shusuke Yoshimoto (Stanford Univ., U.S.A.), Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi (Kobe Univ., Japan), Koji Tsunoda, Toshihiro Sugii (Low-Power Electronics Association and Project (LEAP), Japan) |
Page | pp. 8 - 9 |
Detailed information (abstract, keywords, etc) | |
Slides |
Title | A High Stability, Low Supply Voltage and Low Standby Power Six-Transistor CMOS SRAM |
Author | *Nobuaki Kobayashi, Ryusuke Ito, Tadayoshi Enomoto (Chuo Univ., Japan) |
Page | pp. 10 - 11 |
Detailed information (abstract, keywords, etc) | |
Slides |
Title | An Efficient Multi-Port Memory Controller for Multimedia Applications |
Author | *Xuan-Thuan Nguyen, Cong-Kha Pham (Univ. of Electro-Communications, Japan) |
Page | pp. 12 - 13 |
Detailed information (abstract, keywords, etc) |
Title | Reliability-Configurable Mixed-Grained Reconfigurable Array Compatible with High-Level Synthesis |
Author | *Masanori Hashimoto, Dawood Alnajjar, Hiroaki Konoura (Osaka Univ./JST, CREST, Japan), Yukio Mitsuyama (Kochi Univ. of Tech./JST, CREST, Japan), Hajime Shimada (Nagoya Univ./JST, CREST, Japan), Kazutoshi Kobayashi (Kyoto Inst. of Tech./JST, CREST, Japan), Hiroyuki Kanbara (ASTEM/JST, CREST, Japan), Hiroyuki Ochi (Ritsumeikan Univ./JST, CREST, Japan), Takashi Imagawa (Kyoto Univ./JST, CREST, Japan), Kazutoshi Wakabayashi (NEC/JST, CREST, Japan), Takao Onoye (Osaka Univ./JST, CREST, Japan), Hidetoshi Onodera (Kyoto Univ./JST, CREST, Japan) |
Page | pp. 14 - 15 |
Detailed information (abstract, keywords, etc) | |
Slides |
Title | A 14μA ECG Processor with Noise Tolerant Heart Rate Extractor and FeRAM for Wearable Healthcare Systems |
Author | *Yozaburo Nakai, Shintaro Izumi, Ken Yamashita, Masanao Nakano, Hiroshi Kawaguchi, Masahiko Yoshimoto (Kobe Univ., Japan) |
Page | pp. 16 - 17 |
Detailed information (abstract, keywords, etc) | |
Slides |
Title | A 128-Way FPGA Platform for the Acceleration of KLMS Algorithm |
Author | *Xiaowei Ren, Qihang Yu, Badong Chen, Nanning Zheng, Pengju Ren (Xi'an Jiaotong Univ., China) |
Page | pp. 18 - 19 |
Detailed information (abstract, keywords, etc) | |
Slides |
Title | A Real-Time Permutation Entropy Computation for EEG Signals |
Author | *Xiaowei Ren, Qihang Yu, Badong Chen, Nanning Zheng, Pengju Ren (Xi'an Jiaotong Univ., China) |
Page | pp. 20 - 21 |
Detailed information (abstract, keywords, etc) | |
Slides |
Title | A High Efficient Hardware Architecture for Multiview 3DTV |
Author | *Jiang Yu, Geng Liu, Xin Zhang, Pengju Ren (Xi'an Jiaotong Univ., China) |
Page | pp. 22 - 23 |
Detailed information (abstract, keywords, etc) | |
Slides |
Title | Design of A Scalable Many-Core Processor for Embedded Applications |
Author | *Hsiao-Wei Chien, Jyun-Long Lai, Chao-Chieh Wu, Chih-Tsun Huang, Ting-Shuo Hsu, Jing-Jia Liou (National Tsing Hua Univ., Taiwan) |
Page | pp. 24 - 25 |
Detailed information (abstract, keywords, etc) |
Title | A DPA/DEMA/LEMA-Resistant AES Cryptographic Processor with Supply-Current Equalizer and Micro EM Probe Sensor |
Author | *Daisuke Fujimoto, Noriyuki Miura (Kobe Univ., Japan), Yu-ichi Hayashi, Naofumi Homma, Takafumi Aoki (Tohoku Univ., Japan), Makoto Nagata (Kobe Univ., Japan) |
Page | pp. 26 - 27 |
Detailed information (abstract, keywords, etc) |
Title | A 64×64 1200fps Dual-Mode CMOS Ion-Image Sensor for Accurate DNA Sequencing |
Author | *Xiwei Huang, Jing Guo, Mei Yan, Hao Yu (Nanyang Technological Univ., Singapore) |
Page | pp. 28 - 29 |
Detailed information (abstract, keywords, etc) | |
Slides |
Title | A 0.21-V Minimum Input, 73.6% Maximum Efficiency, Fully Integrated 3-Terminal Voltage Converter with MPPT for Low-Voltage Energy Harvesters |
Author | *Toshihiro Ozaki, Tetsuya Hirose, Takahiro Nagai, Keishi Tsubaki, Nobutaka Kuroki, Masahiro Numa (Kobe Univ., Japan) |
Page | pp. 30 - 31 |
Detailed information (abstract, keywords, etc) | |
Slides |
Title | Dual-Output Wireless Power Delivery System for Small Size Large Volume Wireless Memory Card |
Author | *Junki Hashiba, Toru Kawajiri, Yuya Hasegawa, Hiroki Ishikuro (Keio Univ., Japan) |
Page | pp. 32 - 33 |
Detailed information (abstract, keywords, etc) | |
Slides |
Title | A Tri-Level 50MS/s 10-bit Capacitive-DAC for Bluetooth Applications |
Author | *Daisuke Kanemoto (Univ. of Yamanashi, Japan), Keigo Oshiro, Keiji Yoshida, Haruichi Kanaya (Kyushu Univ., Japan) |
Page | pp. 34 - 35 |
Detailed information (abstract, keywords, etc) |
Title | A Tail-Current Modulated VCO with Adaptive-Bias Scheme |
Author | *Aravind Tharayil Narayanan, Wei Deng, Kenichi Okada, Akira Matsuzawa (Tokyo Inst. of Tech., Japan) |
Page | pp. 36 - 37 |
Detailed information (abstract, keywords, etc) | |
Slides |
Title | A Low-Power VCO Based ADC with Asynchronous Sigma-Delta Modulator in 65nm CMOS |
Author | *Jili Zhang, Chenluan Wang, Shengxi Diao, Fujiang Lin (Univ. of Science and Tech. of China, China) |
Page | pp. 38 - 39 |
Detailed information (abstract, keywords, etc) | |
Slides |
Title | A 0.5-V 5.8-GHz Low-Power Asymmetrical QPSK/OOK Transceiver for Wireless Sensor Network |
Author | *Sho Ikeda, Sang_yeop Lee, Shin Yonezawa, Yiming Fang, Motohiro Takayasu, Taisuke Hamada, Yosuke Ishikawa, Hiroyuki Ito, Noboru Ishihara, Kazuya Masu (Tokyo Inst. of Tech., Japan) |
Page | pp. 40 - 41 |
Detailed information (abstract, keywords, etc) | |
Slides |
Title | A 58.3-to-65.4 GHz 34.2 mW Sub-Harmonically Injection-Locked PLL with a Sub-Sampling Phase Detection |
Author | *Teerachot Siriburanon, Tomohiro Ueno, Kento Kimura, Satoshi Kondo, Wei Deng, Kenichi Okada, Akira Matsuzawa (Tokyo Inst. of Tech., Japan) |
Page | pp. 42 - 43 |
Detailed information (abstract, keywords, etc) |
Title | Circuit and Package Design for 44GB/s Inductive-Coupling DRAM/SoC Interface |
Author | *Akira Okada, Abdul Raziz Junaidi, Yasuhiro Take, Atsutake Kosuge, Tadahiro Kuroda (Keio Univ., Japan) |
Page | pp. 44 - 45 |
Detailed information (abstract, keywords, etc) | |
Slides |
Title | Design and Analysis for ThruChip Design for Manufacturing (DFM) |
Author | *Li-Chung Hsu, Yasuhiro Take, Atsutake Kosuge, So Hasegawa, Junichiro Kadamoto, Tadahiro Kuroda (Keio Univ., Japan) |
Page | pp. 46 - 47 |
Detailed information (abstract, keywords, etc) | |
Slides |
Title | A Novel Approach Using a Minimum Cost Maximum Flow Algorithm for Fault-Tolerant Topology Reconfiguration in NoC Architectures |
Author | Leibo Liu, *Yu Ren, Chenchen Deng (Tsinghua Univ., China), Jie Han (Univ. of Alberta, Canada), Shouyi Yin, Shaojun Wei (Tsinghua Univ., China) |
Page | pp. 48 - 53 |
Detailed information (abstract, keywords, etc) | |
Slides |
Title | Adaptive Remaining Hop Count Flow Control: Consider the Interaction between Packets |
Author | *Peng Wang, Sheng Ma, Hongyi Lu, Zhiying Wang, Chen Li (National Univ. of Defense Tech., China) |
Page | pp. 54 - 60 |
Detailed information (abstract, keywords, etc) | |
Slides |
Title | A Flexible Hardware Barrier Mechanism for Many-Core Processors |
Author | *Takeshi Soga (ISIT Kyushu, JST CREST, Japan), Hiroshi Sasaki, Tomoya Hirao (Kyushu Univ., Japan), Masaaki Kondo (Univ. of Tokyo, Japan), Koji Inoue (Kyushu Univ., Japan) |
Page | pp. 61 - 68 |
Detailed information (abstract, keywords, etc) | |
Slides |
Title | A Performance Enhanced Dual-Switch Network-on-Chip Architecture |
Author | *Lian Zeng, Takahiro Watanabe (Waseda Univ., Japan) |
Page | pp. 69 - 74 |
Detailed information (abstract, keywords, etc) | |
Slides |
Title | A Cross-Layer Framework for Designing and Optimizing Deeply-Scaled FinFET-Based SRAM Cells under Process Variations |
Author | *Alireza Shafaei, Shuang Chen, Yanzhi Wang, Massoud Pedram (Univ. of Southern California, U.S.A.) |
Page | pp. 75 - 80 |
Detailed information (abstract, keywords, etc) | |
Slides |
Title | Controlled Placement of Standard Cell Memory Arrays for High Density and Low Power in 28nm FD-SOI |
Author | *Adam Teman (EPFL, Switzerland), Davide Rossi (Univ. of Bologna, Italy), Pascal Meinerzhagen (EPFL, Switzerland), Luca Benini (Univ. of Bologna, Italy/ETH, Switzerland), Andreas Burg (EPFL, Switzerland) |
Page | pp. 81 - 86 |
Detailed information (abstract, keywords, etc) | |
Slides |
Title | Microarchitectural-Level Statistical Timing Models for Near-Threshold Circuit Design |
Author | *Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera (Kyoto Univ., Japan) |
Page | pp. 87 - 93 |
Detailed information (abstract, keywords, etc) |
Title | Stress-Aware P/G TSV Planning in 3D-ICs |
Author | *Shengcheng Wang, Farshad Firouzi, Fabian Oboril, Mehdi B. Tahoori (Karlsruhe Inst. of Tech., Germany) |
Page | pp. 94 - 99 |
Detailed information (abstract, keywords, etc) | |
Slides |
Title | Quantitative Modeling of Racetrack Memory, A Tradeoff among Area, Performance, and Power |
Author | *Chao Zhang, Guangyu Sun, Weiqi Zhang (Peking Univ., China), Fan Mi, Hai Li (Univ. of Pittsburgh, U.S.A.), Weisheng Zhao (Beihang Univ., China) |
Page | pp. 100 - 105 |
Detailed information (abstract, keywords, etc) | |
Slides |
Title | Technological Exploration of RRAM Crossbar Array for Matrix-Vector Multiplication |
Author | *Peng Gu, Boxun Li, Tianqi Tang (Tsinghua Univ., China), Shimeng Yu, Yu Cao (Arizona State Univ., U.S.A.), Yu Wang, Huazhong Yang (Tsinghua Univ., China) |
Page | pp. 106 - 111 |
Detailed information (abstract, keywords, etc) |
Title | Modeling Framework for Cross-Point Resistive Memory Design Emphasizing Reliability and Variability Issues |
Author | Yang Zheng, Cong Xu (Pennsylvania State Univ., U.S.A.), *Yuan Xie (Pennsylvania State Univ./Univ. of California, Santa Barbara, U.S.A.) |
Page | pp. 112 - 117 |
Detailed information (abstract, keywords, etc) |
Title | A Defect-Aware Approach for Mapping Reconfigurable Single-Electron Transistor Arrays |
Author | *Ching-Yi Huang, Chian-Wei Liu, Chun-Yao Wang (National Tsing Hua Univ., Taiwan), Yung-Chih Chen (Yuan Ze Univ., Taiwan), Suman Datta, Vijaykrishnan Narayanan (Pennsylvania State Univ., U.S.A.) |
Page | pp. 118 - 123 |
Detailed information (abstract, keywords, etc) | |
Slides |
Title | (Invited Paper) Powering the IoT: Storage-Less and Converter-Less Energy Harvesting |
Author | *Hyung Gyu Lee (Daegu Univ., Republic of Korea), Naehyuck Chang (KAIST, Republic of Korea) |
Page | pp. 124 - 129 |
Detailed information (abstract, keywords, etc) |
Title | (Invited Paper) Distributed Computing in IoT: System-on-a-Chip for Smart Cameras as an Example |
Author | *Shao-Yi Chien, Wei-Kai Chan, Yu-Hsiang Tseng (National Taiwan Univ., Taiwan), Chia-Han Lee (Academia Sinica, Taiwan), V. Srinivasa Somayazulu, Yen-Kuang Chen (Intel, U.S.A.) |
Page | pp. 130 - 135 |
Detailed information (abstract, keywords, etc) |
Title | (Invited Paper) Data Sensing and Analysis: Challenges for Wearables |
Author | James Williamson, Qi Liu, Fenglong Lu, Wyatt Mohrman, Kun Li (Univ. of Colorado Boulder, U.S.A.), Robert P. Dick (Univ. of Michigan, U.S.A.), *Li Shang (Univ. of Colorado Boulder, U.S.A.) |
Page | pp. 136 - 141 |
Detailed information (abstract, keywords, etc) |
Title | ShuttleNoC: Boosting On-Chip Communication Efficiency by Enabling Localized Power Adaptation |
Author | Hang Lu (Univ. of Chinese Academy of Sciences, China), *Guihai Yan, Yinhe Han, Ying Wang (Chinese Academy of Sciences, China), Xiaowei Li (Univ. of Chinese Academy of Sciences, China) |
Page | pp. 142 - 147 |
Detailed information (abstract, keywords, etc) |
Title | Energy-Efficient Optical Crossbars on Chip with Multi-Layer Deposited Silicon |
Author | Hui LI, *Sébastien Le Beux (Lyon Institute of Nanotechnology, France), Gabriela Nicolescu (Ecole Polytechnique de Montréal, Canada), Ian O'Connor (Lyon Institute of Nanotechnology, France) |
Page | pp. 148 - 153 |
Detailed information (abstract, keywords, etc) |
Title | Two-Phase Protocol Converters for 3D Asynchronous 1-of-n Data Links |
Author | Julian Hilgemberg Pontes, *Pascal Vivet, Yvain Thonnart (CEA/LETI, France) |
Page | pp. 154 - 159 |
Detailed information (abstract, keywords, etc) | |
Slides |
Title | Fine-Grained Runtime Power Budgeting for Networks-on-Chip |
Author | *Xiaohang Wang, Tengfei Wang (Chinese Academy of Sciences, China), Terrence Mak (Chinese Academy of Sciences/Chinese Univ. of Hong Kong, China), Mei Yang, Yingtao Jiang (Univ. of Nevada, Las Vegas, U.S.A.), Masoud Daneshtalab (Royal Inst. of Tech, Sweden/Univ. of Turku, Finland) |
Page | pp. 160 - 165 |
Detailed information (abstract, keywords, etc) | |
Slides |
Title | Nonvolatile Memory Allocation and Hierarchy Optimization for High-Level Synthesis |
Author | Shuangchen Li (Tsinghua Univ., China/Univ. of California, Santa Barbara, U.S.A.), Ang Li, Yongpan Liu (Tsinghua Univ., China), *Yuan Xie (Univ. of California, Santa Barbara, U.S.A.), Huazhong Yang (Tsinghua Univ., China) |
Page | pp. 166 - 171 |
Detailed information (abstract, keywords, etc) |
Title | Reverse BDD-Based Synthesis for Splitter-Free Optical Circuits |
Author | Robert Wille, *Oliver Keszocze, Clemens Hopfmuller, Rolf Drechsler (Univ. of Bremen, Germany) |
Page | pp. 172 - 177 |
Detailed information (abstract, keywords, etc) | |
Slides |
Title | Determining the Minimal Number of SWAP Gates for Multi-Dimensional Nearest Neighbor Quantum Circuits |
Author | Aaron Lye (Univ. of Bremen, Germany), *Robert Wille, Rolf Drechsler (Univ. of Bremen/Cyber Physical Systems, DFKI GmbH, Germany) |
Page | pp. 178 - 183 |
Detailed information (abstract, keywords, etc) | |
Slides |
Title | Design and Optimization of 3D Digital Microfluidic Biochips for the Polymerase Chain Reaction |
Author | Zipeng Li (Duke Univ., U.S.A.), Tsung-Yi Ho (National Chiao Tung Univ., Taiwan), *Krishnendu Chakrabarty (Duke Univ., U.S.A.) |
Page | pp. 184 - 189 |
Detailed information (abstract, keywords, etc) | |
Slides |
Title | An Accurate and Low Cost PM2.5 Estimation Method Based on Artificial Neural Network |
Author | *Lixue Xia, Rong Luo, Bin Zhao, Yu Wang, Huazhong Yang (Tsinghua Univ., China) |
Page | pp. 190 - 195 |
Detailed information (abstract, keywords, etc) | |
Slides |
Title | Iterative Disparity Voting Based Stereo Matching Algorithm and Its Hardware Implementation |
Author | Zhi Hu, *Yibo Fan, Xiaoyang Zeng (Fudan Univ., China) |
Page | pp. 196 - 201 |
Detailed information (abstract, keywords, etc) | |
Slides |
Title | Obstacle-Avoiding Wind Turbine Placement for Power-Loss and Wake-Effect Optimization |
Author | *Yu-Wei Wu (National Cheng Kung Univ., Taiwan), Yi-yu Shi (Missouri Univ. of Science and Tech., U.S.A.), Sudip Roy (National Cheng Kung Univ., Taiwan), Tsung-Yi Ho (National Chiao Tung Univ., Taiwan) |
Page | pp. 202 - 207 |
Detailed information (abstract, keywords, etc) | |
Slides |
Title | (Invited Paper) An Efficient Linear Time Triple Patterning Solver |
Author | Haitong Tian (Univ. of Illinois, Urbana-Champaign, U.S.A.), Hongbo Zhang (Synopsys, U.S.A.), Zigang Xiao, *Martin D. F. Wong (Univ. of Illinois, Urbana-Champaign, U.S.A.) |
Page | pp. 208 - 213 |
Detailed information (abstract, keywords, etc) |
Title | (Invited Paper) Gate Sizing and Threshold Voltage Assignment for High Performance Microprocessor Designs |
Author | Tiago Reimann (Univ. Federal do Rio Grande do Sul, Brazil), Cliff C.N. Sze (IBM, U.S.A.), *Ricardo Reis (Univ. Federal do Rio Grande do Sul, Brazil) |
Page | pp. 214 - 219 |
Detailed information (abstract, keywords, etc) | |
Slides |
Title | (Invited Paper) Analytical Placement for Rectilinear Blocks |
Author | *Yasuhiro Takashima (Univ. of Kitakyushu, Japan) |
Page | pp. 220 - 225 |
Detailed information (abstract, keywords, etc) | |
Slides |
Title | (Invited Paper) IR to Routing Challenge and Solution for Interposer-Based Design |
Author | *Eric Jia-Wei Fang, Terry Chi-Jih Shih, Darton Shen-Yu Huang (MediaTek, Taiwan) |
Page | pp. 226 - 230 |
Detailed information (abstract, keywords, etc) |
Title | Aging Mitigation in Memory Arrays Using Self-Controlled Bit-Flipping Technique |
Author | *Anteneh Gebregiorgis (TU Delft, Netherlands), Mojtaba Ebrahimi, Saman Kiamehr, Fabian Oboril (Karlsruhe Inst. of Tech., Germany), Said Hamdioui (TU Delft, Netherlands), Mehdi Tahoori (Karlsruhe Inst. of Tech., Germany) |
Page | pp. 231 - 236 |
Detailed information (abstract, keywords, etc) |
Title | Design Methodology for Approximate Accumulator Based on Statistical Error Model |
Author | Chang Liu, *Xinghua Yang, Fei Qiao, Qi Wei, Huazhong Yang (Tsinghua Univ., China) |
Page | pp. 237 - 242 |
Detailed information (abstract, keywords, etc) | |
Slides |
Title | Multiple Independent Gate FETs: How Many Gates Do We Need? |
Author | *Luca Amaru (Integrated Systems Laboratory - EPFL, Switzerland), Gage Hills (Stanford Univ., U.S.A.), Pierre-Emmanuel Gaillardon (Integrated Systems Laboratory - EPFL, Switzerland), Subhasish Mitra (Stanford Univ., U.S.A.), Giovanni De Micheli (Integrated Systems Laboratory - EPFL, Switzerland) |
Page | pp. 243 - 248 |
Detailed information (abstract, keywords, etc) | |
Slides |
Title | Polynomial Time Algorithm for Area and Power Efficient Adder Synthesis in High-Performance Designs |
Author | Subhendu Roy (Univ. of Texas, Austin, U.S.A.), Mihir Choudhury, Ruchir Puri (IBM, U.S.A.), *David Z Pan (Univ. of Texas, Austin, U.S.A.) |
Page | pp. 249 - 254 |
Detailed information (abstract, keywords, etc) |
Title | Accelerating SAT-Based Boolean Matching for Heterogeneous FPGAs Using One-Hot Encoding and CEGAR Technique |
Author | *Yusuke Matsunaga (Kyushu Univ., Japan) |
Page | pp. 255 - 260 |
Detailed information (abstract, keywords, etc) |
Title | Negotiation-Based Task Scheduling and Storage Control Algorithm to Minimize User’s Electric Bills under Dynamic Prices |
Author | Ji Li, Yanzhi Wang, Xue Lin, Shahin Nazarian, *Massoud Pedram (USC, U.S.A.) |
Page | pp. 261 - 266 |
Detailed information (abstract, keywords, etc) | |
Slides |
Title | Many-to-Many Active Cell Balancing Strategy Design |
Author | *Matthias Kauer, Swaminathan Narayanaswamy, Sebastian Steinhorst, Martin Lukasiewycz (TUM CREATE, Singapore), Samarjit Chakraborty (TU Munich, Germany) |
Page | pp. 267 - 272 |
Detailed information (abstract, keywords, etc) |
Title | Intra-Vehicle Network Routing Algorithm for Wiring Weight and Wireless Transmit Power Minimization |
Author | *Ta-Yang Huang, Chia-Jui Chang (National Cheng Kung Univ., Taiwan), Chung-Wei Lin (Univ. of California, Berkeley, U.S.A.), Sudip Roy (National Cheng Kung Univ., Taiwan), Tsung-Yi Ho (National Chiao Tung Univ., Taiwan) |
Page | pp. 273 - 278 |
Detailed information (abstract, keywords, etc) |
Title | An Autonomous Decentralized Mechanism for Energy Interchanges with Accelerated Diffusion Based on MCMC |
Author | *Yusuke Sakumoto (Tokyo Metropolitan Univ., Japan), Ittetsu Taniguchi (Ritsumeikan Univ., Japan) |
Page | pp. 279 - 284 |
Detailed information (abstract, keywords, etc) | |
Slides |
Wednesday, January 21, 2015 |
Title | (Keynote Address) Programmable Network |
Author | *Atsushi Takahara (NTT, Japan) |
Page | p. 285 |
Detailed information (abstract, keywords, etc) |
Title | (Invited Paper) Machine Learning and Pattern Matching in Physical Design |
Author | Bei Yu, *David Z. Pan (Univ. of Texas, Austin, U.S.A.), Tetsuaki Matsunawa (Toshiba, Japan), Xuan Zeng (Fudan Univ., China) |
Page | pp. 286 - 293 |
Detailed information (abstract, keywords, etc) |
Title | (Invited Paper) Self-Learning and Adaptive Board-Level Functional Fault Diagnosis |
Author | Fangming Ye, *Krishnendu Chakrabarty (Duke Univ., U.S.A.), Zhaobo Zhang, Xinli Gu (Huawei Technologies, U.S.A.) |
Page | pp. 294 - 301 |
Detailed information (abstract, keywords, etc) |
Title | (Invited Paper) Fast Statistical Analysis of Rare Failure Events for Memory Circuits in High-Dimensional Variation Space |
Author | Shupeng Sun, *Xin Li (Carnegie Mellon Univ., U.S.A.) |
Page | pp. 302 - 307 |
Detailed information (abstract, keywords, etc) | |
Slides |
Title | (Invited Paper) Data Mining in Functional Test Content Optimization |
Author | *Li-C. Wang (Univ. of California, Santa Barbara, U.S.A.) |
Page | pp. 308 - 315 |
Detailed information (abstract, keywords, etc) |
Title | Checkpoint-Aware Instruction Scheduling for Nonvolatile Processor with Multiple Functional Units |
Author | Mimi Xie, Chen Pan, *Jingtong Hu (Oklahoma State Univ., U.S.A.), Chengmo Yang (Univ. of Delaware, U.S.A.), Yiran Chen (Univ. of Pittsburgh, U.S.A.) |
Page | pp. 316 - 321 |
Detailed information (abstract, keywords, etc) | |
Slides |
Title | Balloonfish: Utilizing Morphable Resistive Memory in Mobile Virtualization |
Author | Linbo Long, Duo Liu, *Xiao Zhu, Kan Zhong (Chongqing Univ., China), Zili Shao (Hong Kong Polytechnic Univ., Hong Kong), Edwin H.-M. Sha (Chongqing Univ., China) |
Page | pp. 322 - 327 |
Detailed information (abstract, keywords, etc) |
Title | A Three-Stage-Write Scheme with Flip-Bit for PCM Main Memory |
Author | Yanbin Li, *Xin Li, Lei Ju, Zhiping Jia (Shandong Univ., China) |
Page | pp. 328 - 333 |
Detailed information (abstract, keywords, etc) | |
Slides |
Title | A Garbage Collection Aware Stripping Method for Solid-State Drives |
Author | *Min Huang (Harbin Inst. of Tech., China), Yi Wang (Shenzhen Univ./Hong Kong Polytechnic Univ., China), Zhaoqing Liu, Liyan Qiao (Harbin Inst. of Tech., China), Zili Shao (Hong Kong Polytechnic Univ., Hong Kong) |
Page | pp. 334 - 339 |
Detailed information (abstract, keywords, etc) |
Title | Unified Non-Volatile Memory and NAND Flash Memory Architecture in Smartphones |
Author | *Renhai Chen (Hong Kong Polytechnic Univ., Hong Kong), Yi Wang (Shenzhen Univ., China), Jingtong Hu (Oklahoma State Univ., U.S.A.), Duo Liu (Chongqing Univ., China), Zili Shao (Hong Kong Polytechnic Univ., Hong Kong), Yong Guan (Capital Normal Univ., China) |
Page | pp. 340 - 345 |
Detailed information (abstract, keywords, etc) |
Title | A Retargetable and Accurate Methodology for Logic-IP-Internal Electromigration Assessment |
Author | Palkesh Jain (Qualcomm India Pvt, India), *Sachin S. Sapatnekar (Univ. of Minnesota, U.S.A.), Jordi Cortadella (Univ. Politècnica de Catalunya, Spain) |
Page | pp. 346 - 351 |
Detailed information (abstract, keywords, etc) |
Title | New Electromigration Modeling and Analysis Considering Time-Varying Temperature and Current Densities |
Author | Hai-Bao Chen, *Sheldon X.-D. Tan, Xin Huang (Univ. of California, Riverside, U.S.A.), Valeriy Sukharev (Mentor Graphics, U.S.A.) |
Page | pp. 352 - 357 |
Detailed information (abstract, keywords, etc) |
Title | Generating Circuit Current Constraints to Guarantee Power Grid Safety |
Author | *Zahi Moudallal, Farid N Najm (Univ. of Toronto, Canada) |
Page | pp. 358 - 365 |
Detailed information (abstract, keywords, etc) | |
Slides |
Title | BEE: Predicting Realistic Worst Case and Stochastic Eye Diagrams by Accounting for Correlated Bitstreams and Coding Strategies |
Author | Aadithya Karthik (UC Berkeley, U.S.A.), Sayak Ray (Princeton Univ., U.S.A.), *Jaijeet Roychowdhury (UC Berkeley, U.S.A.) |
Page | pp. 366 - 371 |
Detailed information (abstract, keywords, etc) |
Title | A Fast Parallel Approach for Common Path Pessimism Removal |
Author | *Chung-Hao Tsai, Wai-Kei Mak (National Tsing Hua Univ., Taiwan) |
Page | pp. 372 - 377 |
Detailed information (abstract, keywords, etc) |
Title | Detailed-Routing-Driven Analytical Standard-Cell Placement |
Author | *Chau-Chin Huang, Chien-Hsiung Chiou, Kai-Han Tseng, Yao-Wen Chang (National Taiwan Univ., Taiwan) |
Page | pp. 378 - 383 |
Detailed information (abstract, keywords, etc) |
Title | An Approach to Anchoring and Placing High Performance Custom Digital Designs |
Author | *Shih-Ying Liu (National Chiao Tung Univ./MediaTek, Taiwan), Tung-Chieh Chen (Synopsys, Taiwan), Hung-Ming Chen (National Chiao Tung Univ., Taiwan) |
Page | pp. 384 - 389 |
Detailed information (abstract, keywords, etc) |
Title | Non-Stitch Triple Patterning-Aware Routing Based on Conflict Graph Pre-Coloring |
Author | *Po-Ya Hsu, Yao-Wen Chang (National Taiwan Univ., Taiwan) |
Page | pp. 390 - 395 |
Detailed information (abstract, keywords, etc) | |
Slides |
Title | Cut Mask Optimization with Wire Planning in Self-Aligned Multiple Patterning Full-Chip Routing |
Author | *Shao-Yun Fang (National Taiwan Univ. of Science and Tech., Taiwan) |
Page | pp. 396 - 401 |
Detailed information (abstract, keywords, etc) | |
Slides |
Title | A Length Matching Routing Method for Disordered Pins in PCB Design |
Author | *Ran Zhang, Tieyuan Pan, Li Zhu, Takahiro Watanabe (Waseda Univ., Japan) |
Page | pp. 402 - 407 |
Detailed information (abstract, keywords, etc) | |
Slides |
Title | (Invited Paper) Systems Modeling for Additional Development in Automotive E/E Architecture |
Author | *Hidekazu Nishimura (Keio Univ., Japan) |
Page | pp. 408 - 409 |
Detailed information (abstract, keywords, etc) |
Title | (Invited Paper) Implementation and Evaluation of Image Recognition Algorithm for An Intelligent Vehicle using Heterogeneous Multi-Core SoC |
Author | *Nau Ozaki, Masato Uchiyama, Yasuki Tanabe, Shuichi Miyazaki, Takaaki Sawada, Takanori Tamai, Moriyasu Banno (Toshiba, Japan) |
Page | pp. 410 - 415 |
Detailed information (abstract, keywords, etc) |
Title | (Invited Paper) Trend in Power Devices for Electric and Hybrid Electric Vehicles |
Author | *Khalid Hussein, Akira Fujita, Katsumi Sato (Mitsubishi Electric, Japan) |
Page | p. 416 |
Detailed information (abstract, keywords, etc) |
Title | Multilane Racetrack Caches: Improving Efficiency Through Compression and Independent Shifting |
Author | *Haifeng Xu (Univ. of Pittsburgh, U.S.A.), Yong Li (VMware, U.S.A.), Rami Melhem, Alex K. Jones (Univ. of Pittsburgh, U.S.A.) |
Page | pp. 417 - 422 |
Detailed information (abstract, keywords, etc) | |
Slides |
Title | Managing Hybrid On-Chip Scratchpad and Cache Memories for Multi-Tasking Embedded Systems |
Author | Zimeng Zhou, *Lei Ju, Zhiping Jia, Xin Li (Shandong Univ., China) |
Page | pp. 423 - 428 |
Detailed information (abstract, keywords, etc) | |
Slides |
Title | Optimizing Thread-to-Core Mapping on Manycore Platforms with Distributed Tag Directories |
Author | *Guantao Liu, Tim Schmidt, Rainer Doemer (Univ. of California, Irvine, U.S.A.), Ajit Dingankar, Desmond Kirkpatrick (Intel, U.S.A.) |
Page | pp. 429 - 434 |
Detailed information (abstract, keywords, etc) | |
Slides |
Title | Accelerating Non-Volatile/Hybrid Processor Cache Design Space Exploration for Application Specific Embedded Systems |
Author | *Mohammad Shihabul Haque, Ang Li, Akash Kumar (National Univ. of Singapore, Singapore), Qingsong Wei (Data Storage Institute, Singapore) |
Page | pp. 435 - 440 |
Detailed information (abstract, keywords, etc) |
Title | Accurate Passivity-Enforced Macromodeling for RF Circuits via Iterative Zero/Pole Update Based on Measurement Data |
Author | Ying-Chih Wang, Shihui Yin, Minhee Jun, *Xin Li, Lawrence T. Pileggi, Tamal Mukherjee, Rohit Negi (Carnegie Mellon Univ., U.S.A.) |
Page | pp. 441 - 446 |
Detailed information (abstract, keywords, etc) | |
Slides |
Title | Physical Verification Flow for Hierarchical Analog IC Design Constraints |
Author | *Volker Meyer zu Bexten, Markus Tristl (Infineon Technologies AG, Germany), Göran Jerke (Robert Bosch GmbH, Germany), Hartmut Marquardt (Mentor Graphics, Germany), Dina Medhat (Mentor Graphics, Egypt) |
Page | pp. 447 - 453 |
Detailed information (abstract, keywords, etc) | |
Slides |
Title | Automatic Design for Analog/RF Front-End System in 802.11ac Receiver |
Author | *Zhijian Pan, Chuan Qin, Zuochang Ye, Yan Wang (Tsinghua Univ., China) |
Page | pp. 454 - 459 |
Detailed information (abstract, keywords, etc) |
Title | SIPredict: Efficient Post-Layout Waveform Prediction via System Identification |
Author | *Qicheng Huang, Xiao Li, Fan Yang, Xuan Zeng (Fudan Univ., China), Xin Li (Fudan Univ., China/Carnegie Mellon Univ., U.S.A.) |
Page | pp. 460 - 465 |
Detailed information (abstract, keywords, etc) | |
Slides |
Title | Useful Clock Skew Scheduling Using Adjustable Delay Buffers in Multi-Power Mode Designs |
Author | *Juyeon Kim, Taewhan Kim (Seoul National Univ., Republic of Korea) |
Page | pp. 466 - 471 |
Detailed information (abstract, keywords, etc) | |
Slides |
Title | Fast Clock Skew Scheduling Based on Sparse-Graph Algorithms |
Author | *Rickard Ewetz (Purdue Univ., U.S.A.), Shankarshana Janarthanan (NVIDIA, U.S.A.), Cheng-Kok Koh (Purdue Univ., U.S.A.) |
Page | pp. 472 - 477 |
Detailed information (abstract, keywords, etc) | |
Slides |
Title | Modeling and Optimization of Low Power Resonant Clock Mesh |
Author | *Wulong Liu (Tsinghua Univ., China), Guoqing Chen (Research Lab, Advanced Micro Devices, China), Yu Wang, Huazhong Yang (Tsinghua Univ., China) |
Page | pp. 478 - 483 |
Detailed information (abstract, keywords, etc) | |
Slides |
Title | Synthesis of Resonant Clock Networks Supporting Dynamic Voltage / Frequency Scaling |
Author | *Seyong Ahn, Minseok Kang (Seoul National Univ., Republic of Korea), Marios C. Papaefthymiou (Univ. of Michigan, U.S.A.), Taewhan Kim (Seoul National Univ., Republic of Korea) |
Page | pp. 484 - 489 |
Detailed information (abstract, keywords, etc) | |
Slides |
Title | (Panel Discussion) Challenges in the Era of Big-Data Computing |
Author | Panelists: Kento Aida (NII, Japan), Derek Chiou (Microsoft, U.S.A.), Hiroshi Nakamura (Univ. of Tokyo, Japan), Hiroyuki Tanaka (Nippon Telegraph and Telephone, Japan), Iwao Yamazaki (Fujitsu, Japan) |
Detailed information (abstract, keywords, etc) |
Title | An Efficient STT-RAM-Based Register File in GPU Architectures |
Author | Xiaoxiao Liu, Mengjie Mao, Xiuyuan Bi, Hai Li, *Yiran Chen (Univ. of Pittsburgh, U.S.A.) |
Page | pp. 490 - 495 |
Detailed information (abstract, keywords, etc) | |
Slides |
Title | A Bit-Write Reduction Method based on Error-Correcting Codes for Non-Volatile Memories |
Author | *Masashi Tawada, Shinji Kimura, Masao Yanagisawa, Nozomu Togawa (Waseda Univ., Japan) |
Page | pp. 496 - 501 |
Detailed information (abstract, keywords, etc) |
Title | Minimizing MLC PCM Write Energy for Free through Profiling-Based State Remapping |
Author | *Mengying Zhao (City Univ. of Hong Kong, Hong Kong), Yuan Xue, Chengmo Yang (Univ. of Delaware, U.S.A.), Chun Jason Xue (City Univ. of Hong Kong, Hong Kong) |
Page | pp. 502 - 507 |
Detailed information (abstract, keywords, etc) | |
Slides |
Title | Improving Performance and Lifetime of DRAM-PCM Hybrid Main Memory through a Proactive Page Allocation Strategy |
Author | Hoda Aghaei Khouzani, *Chengmo Yang (Univ. of Delaware, U.S.A.), Jingtong Hu (Oklahoma State Univ., U.S.A.) |
Page | pp. 508 - 513 |
Detailed information (abstract, keywords, etc) |
Title | Enhanced LCCG: A Novel Test Clock Generation Scheme for Faster-than-at-Speed Delay Testing |
Author | *Songwei Pei, Ye Geng (Beijing Univ. of Chemical Tech., China), Huawei Li (Key Laboratory of Computer System and Architecture, Institute of Computing Technology, China), Jun Liu (Hefei Univ. of Tech., China), Song Jin (North China Electric Power Univ., China) |
Page | pp. 514 - 519 |
Detailed information (abstract, keywords, etc) |
Title | An Efficient 3D-IC On-Chip Test Framework to Embed TSV Testing in Memory BIST |
Author | Liang-Che Li, Wen-Hsuan Hsu, *Kuen-Jong Lee (National Cheng Kung Univ., Taiwan), Chun-Lung Hsu (ITRI, Taiwan) |
Page | pp. 520 - 525 |
Detailed information (abstract, keywords, etc) |
Title | An Integrated Temperature-Cycling Acceleration and Test Technique for 3D Stacked ICs |
Author | *Nima Aghaee, Zebo Peng, Petru Eles (Linköping Univ., Sweden) |
Page | pp. 526 - 531 |
Detailed information (abstract, keywords, etc) | |
Slides |
Title | Software-Based Test and Diagnosis of SoCs Using Embedded and Wide-I/O DRAM |
Author | *Sergej Deutsch, Krishnendu Chakrabarty (Duke Univ., U.S.A.) |
Page | pp. 532 - 537 |
Detailed information (abstract, keywords, etc) |
Title | Logic-DRAM Co-Design to Efficiently Repair Stacked DRAM With Unused Spares |
Author | Minjie Lv, *Hongbin Sun, Jingmin Xin, Nanning Zheng (Xi'an Jiaotong Univ., China) |
Page | pp. 538 - 543 |
Detailed information (abstract, keywords, etc) |
Title | Electromigration-Aware Redundant via Insertion |
Author | Jiwoo Pak, Bei Yu, *David Z. Pan (Univ. of Texas, Austin, U.S.A.) |
Page | pp. 544 - 549 |
Detailed information (abstract, keywords, etc) |
Title | Synthesis of Resilient Circuits from Guarded Atomic Actions |
Author | Yuankai Chen (Synopsys, U.S.A.), *Hai Zhou (Northwestern Univ., U.S.A.) |
Page | pp. 550 - 555 |
Detailed information (abstract, keywords, etc) |
Title | Incremental Latin Hypercube Sampling for Lifetime Stochastic Behavioral Modeling of Analog Circuits |
Author | Yen-Lung Chen (National Central Univ., Taiwan), Wei Wu (Univ. of California, Los Angeles, U.S.A.), *Chien-Nan Jimmy Liu (National Central Univ., Taiwan), Lei He (Univ. of California, Los Angeles, U.S.A.) |
Page | pp. 556 - 561 |
Detailed information (abstract, keywords, etc) | |
Slides |
Thursday, January 22, 2015 |
Title | (Keynote Address) When and How Will an AI Be Smart Enough to Design? |
Author | *Noriko Arai (NII, Japan) |
Page | p. 562 |
Detailed information (abstract, keywords, etc) |
Title | (Invited Paper) Toward Large-Scale Access-Transistor-Free Memristive Crossbars |
Author | Amirali Ghofrani, Miguel Angel Lastras-Montaño, *K.-T. Tim Cheng (Univ. of California, Santa Barbara, U.S.A.) |
Page | pp. 563 - 568 |
Detailed information (abstract, keywords, etc) | |
Slides |
Title | (Invited Paper) Read Circuits for Resistive Memory (ReRAM) and Memristor-Based Nonvolatile Logics |
Author | *Meng-Fan Chang, Albert Lee, Chien-Chen Lin (National Tsing Hua Univ., Taiwan), Mon-Shu Ho (National Chung Hsin Univ., Taiwan), Ping-Cheng Chen (I-Shou Univ., Taiwan), Chia-Chen Kuo, Ming-Pin Chen, Pei-Ling Tseng, Tzu-Kun Ku (ITRI, Taiwan), Chien-Fu Chen, Kai-Shin Li, Jia-Min Shieh (National Nano Device Laboratories, Taiwan) |
Page | pp. 569 - 574 |
Detailed information (abstract, keywords, etc) |
Title | (Invited Paper) 3D ReRAM with Field Assisted Super-Linear Threshold (FASTTM) Selector Technology for Super-Dense, Low Power, Low Latency Data Storage Systems |
Author | Sung Hyun Jo, Tanmay Kumar, Mehdi Asnaashari, Wei D. Lu, *Hagop Nazarian (Crossbar, U.S.A.) |
Page | p. 575 |
Detailed information (abstract, keywords, etc) |
Title | (Invited Paper) Modeling and Design Optimization of ReRAM |
Author | *J. F. Kang, H. T. Li, P. Huang, Z. Chen, B. Gao, X. Y. Liu (Peking Univ., China), Z. Z. Jiang, H.-S. P. Wong (Stanford Univ., U.S.A.) |
Page | pp. 576 - 581 |
Detailed information (abstract, keywords, etc) | |
Slides |
Title | Evaluation of Runtime Monitoring Methods for Real-Time Event Streams |
Author | *Biao Hu, Kai Huang, Gang Chen, Alois Knoll (Technical Univ. of Muenchen, Germany) |
Page | pp. 582 - 587 |
Detailed information (abstract, keywords, etc) | |
Slides |
Title | Automatic Timing-Coherent Transactor Generation for Mixed-Level Simulations |
Author | *Li-chun Chen, Hsin-I Wu, Ren-Song Tsay (National Tsing Hua Univ., Taiwan) |
Page | pp. 588 - 593 |
Detailed information (abstract, keywords, etc) | |
Slides |
Title | Hybrid Coverage Assertions for Efficient Coverage Analysis Across Simulation and Emulation Environments |
Author | Hsuan-Ming Chou, Hong-Chang Wu, Yi-Chiao Chen, *Jean Tsao, Shih-Chieh Chang (National Tsing Hua Univ., Taiwan) |
Page | pp. 594 - 599 |
Detailed information (abstract, keywords, etc) | |
Slides |
Title | SWAT: Assertion-Based Debugging of Concurrency Issues at System Level |
Author | *Luis Gabriel Murillo, Róbert Lajos Bücs, Daniel Hincapie, Rainer Leupers, Gerd Ascheid (RWTH Aachen Univ., Germany) |
Page | pp. 600 - 605 |
Detailed information (abstract, keywords, etc) |
Title | Communication Protocol Analysis of Transaction-Level Models Using Satisfiability Modulo Theories |
Author | *Che-Wei Chang, Rainer Doemer (Univ. of California, Irvine, U.S.A.) |
Page | pp. 606 - 611 |
Detailed information (abstract, keywords, etc) | |
Slides |
Title | Guiding Fault-Driven Adaption in Multicore Systems through a Reliability-Aware Static Task Schedule |
Author | Laura A Rozo Duque, *Chengmo Yang (Univ. of Delaware, U.S.A.) |
Page | pp. 612 - 617 |
Detailed information (abstract, keywords, etc) |
Title | Approximation-Aware Scheduling on Heterogeneous Multi-Core Architectures |
Author | *Cheng Tan, Thannirmalai Somu Muthukaruppan, Tulika Mitra (National Univ. of Singapore, Singapore), Lei Ju (Shandong Univ., China) |
Page | pp. 618 - 623 |
Detailed information (abstract, keywords, etc) | |
Slides |
Title | Composing Real-Time Applications from Communicating Black-Box Components |
Author | *Martin Becker (Tech. Univ. of Munich, Germany), Alejandro Masrur (Software Technology for Embedded Systems, Technical Univ. Chemnitz, Germany), Samarjit Chakraborty (Tech. Univ. of Munich, Germany) |
Page | pp. 624 - 629 |
Detailed information (abstract, keywords, etc) | |
Slides |
Title | Enhanced Partitioned Scheduling of Mixed-Criticality Systems on Multicore Platforms |
Author | *Zaid Al-bayati (McGill Univ., Canada), Qingling Zhao (Zhejiang Univ., China), Ahmed Youssef (McGill Univ., Canada), Haibo Zeng (Virginia Tech, U.S.A.), Zonghua Gu (Zhejiang Univ., China) |
Page | pp. 630 - 635 |
Detailed information (abstract, keywords, etc) |
Title | Reducing Dynamic Dispatch Overhead (DDO) of SLDL-Synthesized Embedded Software |
Author | Jiaxing Zhang, Sanyuan Tang, *Gunar Schirner (Northeastern Univ., U.S.A.) |
Page | pp. 636 - 643 |
Detailed information (abstract, keywords, etc) |
Title | Contact Pitch and Location Prediction for Directed Self-Assembly Template Verification |
Author | Zigang Xiao, Yuelin Du, *Martin D.F. Wong (Univ. of Illinois, Urbana-Champaign, U.S.A.), He Yi, H.-S. Philip Wong (Stanford Univ., U.S.A.), Hongbo Zhang (Synopsys, U.S.A.) |
Page | pp. 644 - 651 |
Detailed information (abstract, keywords, etc) | |
Slides |
Title | Layout Decomposition Co-Optimization for Hybrid E-Beam and Multiple Patterning Lithography |
Author | *Yunfeng Yang, Wai-Shing Luk (Fudan Univ., China), Hai Zhou (Fudan Univ., China/Northwestern Univ., U.S.A.), Changhao Yan, Xuan Zeng (Fudan Univ., China), Dian Zhou (Fudan Univ, China/Univ. of Texas, Dallas, U.S.A.) |
Page | pp. 652 - 657 |
Detailed information (abstract, keywords, etc) |
Title | Polynomial Time Optimal Algorithm for Stencil Row Planning in E-Beam Lithography |
Author | Daifeng Guo, Yuelin Du, *Martin D.F. Wong (Univ. of Illinois, Urbana-Champaign, U.S.A.) |
Page | pp. 658 - 664 |
Detailed information (abstract, keywords, etc) |
Title | Fast Mask Assignment Using Positive Semidefinite Relaxation in LELECUT Triple Patterning Lithography |
Author | *Yukihide Kohira (Univ. of Aizu, Japan), Tomomi Matsui (Tokyo Inst. of Tech., Japan), Yoko Yokoyama, Chikaaki Kodama (Toshiba, Japan), Atsushi Takahashi (Tokyo Inst. of Tech., Japan), Shigeki Nojima, Satoshi Tanaka (Toshiba, Japan) |
Page | pp. 665 - 670 |
Detailed information (abstract, keywords, etc) |
Title | Layout Decomposition for Spacer-is-Metal (SIM) Self-Aligned Double Patterning |
Author | *Shao-Yun Fang (National Taiwan Univ. of Science and Tech., Taiwan), Yi-Shu Tai, Yao-Wen Chang (National Taiwan Univ., Taiwan) |
Page | pp. 671 - 676 |
Detailed information (abstract, keywords, etc) | |
Slides |
Title | (Invited Paper) The Prospects of Next Generation Television - Japan’s Initiative to 2020 - |
Author | *Keiya Motohashi (NetTV Forum, Japan) |
Page | pp. 677 - 679 |
Detailed information (abstract, keywords, etc) |
Title | (Invited Paper) 8K LCD : Technologies and Challenges toward the Realization of SUPER Hi-VISION TV |
Author | *Takeshi Kumakura (SHARP, Japan) |
Page | pp. 680 - 683 |
Detailed information (abstract, keywords, etc) |
Title | (Invited Paper) The World's 1st Complete-4K SoC Solution with Hybrid Memory System |
Author | *Daisuke Murakami, Yuki Soga, Daisuke Imoto, Yoshiharu Watanabe, Takashi Yamada (Panasonic, Japan) |
Page | pp. 684 - 686 |
Detailed information (abstract, keywords, etc) |
Title | (Invited Paper) H.265/HEVC Encoder for UHDTV |
Author | *Mitsuo Ikeda (NTT, Japan) |
Page | pp. 687 - 688 |
Detailed information (abstract, keywords, etc) |
Title | An Accurate ACOSSO Metamodeling Technique for Processor Architecture Design Space Exploration |
Author | *Hongwei Wang (Beijing Key Laboratory of Mobile Computing and Pervasive Device/Chinese Academy of Sciences/Univ. of Chinese Academy of Sciences, China), Ziyuan Zhu, Jinglin Shi, Yongtao Su (Beijing Key Laboratory of Mobile Computing and Pervasive Device/Chinese Academy of Sciences, China) |
Page | pp. 689 - 694 |
Detailed information (abstract, keywords, etc) |
Title | Speeding Up Single Pass Simulation of PLRUt Caches |
Author | *Josef Schneider, Jorgen Peddersen, Sri Parameswaran (Univ. of New South Wales, Australia) |
Page | pp. 695 - 700 |
Detailed information (abstract, keywords, etc) | |
Slides |
Title | ADAPT: An ADAptive Manycore Methodology for Software Pipelined ApplicaTions |
Author | *Xi Zhang, Haris Javaid (Univ. of New South Wales, Australia), Muhammad Shafique (Karlsruhe Inst. of Tech., Germany), Jude Angelo Ambrose (Univ. of New South Wales, Australia), Jörg Henkel (Karlsruhe Inst. of Tech., Germany), Sri Parameswaran (Univ. of New South Wales, Australia) |
Page | pp. 701 - 706 |
Detailed information (abstract, keywords, etc) | |
Slides |
Title | A Trace-Driven Approach for Fast and Accurate Simulation of Manycore Architectures |
Author | *Anastasiia Butko, Rafael Garibotti, Luciano Ost, Vianney Lapotre, Abdoulaye Gamatie, Gilles Sassatelli (LIRMM/CNRS/Univ. of Montpellier II, France), Chris Adeniyi-Jones (ARM, U.K.) |
Page | pp. 707 - 712 |
Detailed information (abstract, keywords, etc) | |
Slides |
Title | Compact Modeling of Microbatteries Using Behavioral Linearization and Model-Order Reduction |
Author | Mohammed Shemsu Nesro (Masdar Inst. of Tech., United Arab Emirates), Lizhong Sun (Applied Materials, U.S.A.), *Ibrahim (Abe) M. Elfadel (Masdar Inst. of Science and Tech., United Arab Emirates) |
Page | pp. 713 - 718 |
Detailed information (abstract, keywords, etc) |
Title | GPU-Accelerated Parallel Monte Carlo Analysis of Analog Circuits by Hierarchical Graph-Based Solver |
Author | Yan Zhu, *Sheldon X.-D. Tan (Univ. of California, Riverside, U.S.A.) |
Page | pp. 719 - 724 |
Detailed information (abstract, keywords, etc) |
Title | Automated Generation of Hybrid System Models for Reachability Analysis of Nonlinear Analog Circuits |
Author | *Hyun-Sek Lukas Lee (Leibniz Univ. Hannover, Germany), Matthias Althoff (Tech. Univ. München, Germany), Stefan Hoelldampf, Markus Olbrich, Erich Barke (Leibniz Univ. Hannover, Germany) |
Page | pp. 725 - 730 |
Detailed information (abstract, keywords, etc) |
Title | Area Efficient Device-Parameter Estimation Using Sensitivity-Configurable Ring Oscillator |
Author | *Shoichi Iizuka, Yuma Higuchi, Masanori Hashimoto, Takao Onoye (Osaka Univ., Japan) |
Page | pp. 731 - 736 |
Detailed information (abstract, keywords, etc) | |
Slides |
Title | On Test Syndrome Merging for Reasoning-Based Board-Level Functional Fault Diagnosis |
Author | Zelong Sun (Chinese Univ. of Hong Kong, Hong Kong), *Li Jiang (Shanghai Jiao Tong Univ., China), Qiang Xu (Chinese Univ. of Hong Kong, Hong Kong), Zhaobo Zhang, Zhiyuan Wang, Xinli Gu (Huawei Technologies, U.S.A.) |
Page | pp. 737 - 742 |
Detailed information (abstract, keywords, etc) | |
Slides |
Title | Event-Driven Transient Error Propagation: A Scalable and Accurate Soft Error Rate Estimation Approach |
Author | Mojtaba Ebrahimi, Razi Seyyedi, Liang Chen, *Mehdi Tahoori (Karlsruhe Inst. of Tech., Germany) |
Page | pp. 743 - 748 |
Detailed information (abstract, keywords, etc) |
Title | A Novel Methodology for Testing Hardware Security and Trust Exploiting On-Chip Power Noise Measurement |
Author | *Daisuke Fujimoto, Makoto Nagata (Kobe Univ., Japan), Shivam Bhasin, Jean-Luc Danger (Telecom Paristech, France) |
Page | pp. 749 - 754 |
Detailed information (abstract, keywords, etc) |
Title | Hardware Trojan Detection Using Exhaustive Testing of k-bit Subspaces |
Author | Nicole Lesperance, Shrikant Kulkarni, *Kwang-Ting Cheng (UC Santa Barbara, U.S.A.) |
Page | pp. 755 - 760 |
Detailed information (abstract, keywords, etc) | |
Slides |
Title | (Panel Discussion) IP Base SoC Design and IP Design Innovation |
Author | Panelists: Hironori Ando (Synopsys, Japan), Kevin Yee (Cadence, U.S.A.), Randy Smith (Sonics, U.S.A.), Neil Parris (ARM, U.K.) |
Detailed information (abstract, keywords, etc) |
Title | AROMA: A Highly Accurate Microcomponent-Based Approach for Embedded Processor Power Analysis |
Author | Zih-Ci Huang, *Chi-Kang Chen, Ren-Song Tsay (National Tsing Hua Univ., Taiwan) |
Page | pp. 761 - 766 |
Detailed information (abstract, keywords, etc) | |
Slides |
Title | Battery-Aware Mapping Optimization of Loop Nests for CGRAs |
Author | *Yu Peng, Shouyi Yin, Leibo Liu, Shaojun Wei (Tsinghua Univ., China) |
Page | pp. 767 - 772 |
Detailed information (abstract, keywords, etc) | |
Slides |
Title | THOR: Orchestrated Thermal Management of Cores and Networks in 3D Many-Core Architectures |
Author | *Jinho Lee, Junwhan Ahn, Kiyoung Choi (Seoul National Univ., Republic of Korea), Kyungsu Kang (Samsung Electronics, Republic of Korea) |
Page | pp. 773 - 778 |
Detailed information (abstract, keywords, etc) | |
Slides |
Title | Early Stage Real-Time SoC Power Estimation Using RTL Instrumentation |
Author | Jianlei Yang (Tsinghua Univ./Intel, China), *Liwei Ma, Kang Zhao (Intel, China), Yici Cai (Tsinghua Univ., China), Tin-Fook Ngai (Intel, China) |
Page | pp. 779 - 784 |
Detailed information (abstract, keywords, etc) | |
Slides |
Title | (Invited Paper) Heterogeneous Architecture Design with Emerging 3D and Non-Volatile Memory Technologies |
Author | Qiaosha Zou, Matthew Poremba (Pennsylvania State Univ., U.S.A.), Rui He, Wei Yang, Junfeng Zhao (Huawei Shannon Lab, China), *Yuan Xie (Univ. of California, Santa Barbara, U.S.A.) |
Page | pp. 785 - 790 |
Detailed information (abstract, keywords, etc) |
Title | (Invited Paper) Alleviate Chip I/O Pin Constraints for Multicore Processors through Optical Interconnects |
Author | *Zhehui Wang, Jiang Xu, Peng Yang, Xuan Wang, Zhe Wang, Luan H.K. Duong, Zhifei Wang, Haoran Li, Rafael K.V. Maeda, Xiaowen Wu (Hong Kong Univ. of Science and Tech., Hong Kong), Yaoyao Ye, Qinfen Hao (Huawei Technologies, China) |
Page | pp. 791 - 796 |
Detailed information (abstract, keywords, etc) | |
Slides |
Title | (Invited Paper) A Fast and Accurate Network-on-Chip Timing Simulator with a Flit Propagation Model |
Author | Ting-Shuo Hsu, Jun-Lin Chiu, Chao-Kai Yu, *Jing-Jia Liou (National Tsing Hua Univ., Taiwan) |
Page | pp. 797 - 802 |
Detailed information (abstract, keywords, etc) | |
Slides |
Title | (Invited Paper) Application-Level Embedded Communication Tracer for Many-Core Systems |
Author | *Chih-Tsun Huang, Kuan-Chun Tasi, Jun-Shen Lin, Hsiao-Wei Chien (National Tsing Hua Univ., Taiwan) |
Page | pp. 803 - 808 |
Detailed information (abstract, keywords, etc) |
Title | Timing-Based Anomaly Detection in Embedded Systems |
Author | Sixing Lu, Minjun Seo, *Roman Lysecky (Univ. of Arizona, U.S.A.) |
Page | pp. 809 - 814 |
Detailed information (abstract, keywords, etc) | |
Slides |
Title | Satisfiability Don't Care Condition Based Circuit Fingerprinting Techniques |
Author | *Carson J Dunbar, Gang Qu (Univ. of Maryland, U.S.A.) |
Page | pp. 815 - 820 |
Detailed information (abstract, keywords, etc) | |
Slides |
Title | IC Piracy Prevention via Design Withholding and Entanglement |
Author | Soroush Khaleghi, Kai Da Zhao, *Wenjing Rao (Univ. of Illinois, Chicago, U.S.A.) |
Page | pp. 821 - 826 |
Detailed information (abstract, keywords, etc) | |
Slides |
Title | Vulnerability Analysis for Crypto Devices against Probing Attack |
Author | *Lingxiao Wei, Jie Zhang, Feng Yuan, Yannan Liu (Chinese Univ. of Hong Kong, Hong Kong), Junfeng Fan (Open Security Research, China), Qiang Xu (Chinese Univ. of Hong Kong, Hong Kong) |
Page | pp. 827 - 832 |
Detailed information (abstract, keywords, etc) |