(Go to Top Page)

The 20th Asia and South Pacific Design Automation Conference
Technical Program

Remark: The presenter of each paper is marked with "*".
Technical Program:   SIMPLE version   DETAILED version with abstract
Author Index:   HERE

Session Schedule


Tuesday, January 20, 2015

Room 103Room 102Room 104Room 105
1K  (International Conference Room)
Opening & Keynote I

8:30 - 9:50
1S  University Design Contest
10:20 - 12:10
1A  NoCS I (Performance and Fault Tolerance)
10:20 - 12:00
1B  Toward Power Efficient Design
10:20 - 12:00
1C  Modeling and Design Methodologies of Post-silicon Devices
10:20 - 12:00
2S  (Special Session) Internet of Things
13:50 - 15:30
2A  NoCS II (Power and Emerging Technology)
13:50 - 15:30
2B  Design Automation for Tomorrow’s Circuit Technologies
13:50 - 15:30
2C  Emerging Applications
13:50 - 15:30
3S  (Special Session) New Challenges and Solutions in Nanometer Physical Design
15:50 - 17:30
3A  Circuits for Performance and Reliability
15:50 - 16:40
3B  Frontiers in Logic Synthesis
15:50 - 17:30
3C  Energy Optimization for Electric Vehicles and Smart Grids
15:50 - 17:30



Wednesday, January 21, 2015

Room 103Room 102Room 104Room 105
2K  (International Conference Room)
Keynote II

9:00 - 9:50
4S  (Special Session) Machine Learning in EDA: Promises and Challenges in Selected Applications
10:15 - 12:20
4A  Efficient NVM Management, from Register to Disk
10:15 - 12:20
4B  Robust Timing, and P/G Modeling and Design
10:15 - 12:20
4C  New Issues in Placement and Routing
10:15 - 12:20
5S  (Designers' Forum ) Car Electronics
13:50 - 15:30
5A  Optimization and Exploration for Caches
13:50 - 15:30
5B  CAD for Analog/RF/Mixed-Signal Design
13:50 - 15:30
5C  Next-Generation Clock Network Synthesis
13:50 - 15:30
6S  (Designers' Forum) Panel Discussion: Challenges in the Era of Big-Data Computing
15:50 - 17:30
6A  Optimization Techniques for Non-Volatile Memory based Systems
15:50 - 17:30
6B  Test for Higher Quality
15:50 - 17:30
6C  Reliability
15:50 - 17:30
Banquet (Convention Hall A)
18:00 - 20:00



Thursday, January 22, 2015

Room 103Room 102Room 104Room 105
3K  (International Conference Room)
Keynote III

9:00 - 9:50
7S  (Special Session) The Future of Emerging ReRAM Technology
10:15 - 12:20
7A  Ensuring the Correctness of System Integration
10:15 - 12:20
7B  Orchestrating Tasks, Cores, and Communication
10:15 - 12:20
7C  Design for Manufacturability
10:15 - 12:20
8S  (Designers' Forum) Technology Trend toward 8K Era
13:50 - 15:30
8A  Exploring Better Architecture of Your Systems
13:50 - 15:30
8B  Circuit-Level Modeling and Simulation
13:50 - 15:30
8C  Reliable and Trustworthy Electronics
13:50 - 15:30
9S  (Designers' Forum) Panel Discussion: IP Base SoC Design and IP Design Innovation
15:50 - 17:30
9A  Power/Thermal Management and Modeling
15:50 - 17:30
9B  (Special Session) System-Level Designs and Tools for Multicore Systems
15:50 - 17:30
9C  Building Secure Systems
15:50 - 17:30


List of papers

Remark: The presenter of each paper is marked with "*".

Tuesday, January 20, 2015

Session 1K  Opening & Keynote I
Time: 8:30 - 9:50 Tuesday, January 20, 2015
Location: International Conference Room
Chair: Kunio Uchiyama (Hitachi)

1K-1 (Time: 8:30 - 9:50)
Title(Keynote Address) The Required Technologies for Automotive towards 2020
Author*Udo Wolz (Bosch, Japan)
Pagep. 1
Detailed information (abstract, keywords, etc)


Session 1S  University Design Contest
Time: 10:20 - 12:10 Tuesday, January 20, 2015
Location: Room 103
Chairs: Hiroyuki Ito (Tokyo Inst. of Tech., Japan), Noriyuki Miura (Kobe Univ., Japan)

1S-1 (Time: 10:20 - 10:24)
TitleAn HDL-Synthesized Gated-Edge-Injection PLL with A Current Output DAC
Author*Dongsheng Yang, Wei Deng, Tomohiro Ueno, Teerachot Siriburanon, Satoshi Kondo, Kenichi Okada, Akira Matsuzawa (Tokyo Inst. of Tech., Japan)
Pagepp. 2 - 3
Detailed information (abstract, keywords, etc)
Slides

1S-2 (Time: 10:24 - 10:28)
TitleAn Oscillator-Based True Random Number Generator with Process and Temperature Tolerance
AuthorTakehiko Amaki, *Masanori Hashimoto, Takao Onoye (Osaka Univ., Japan)
Pagepp. 4 - 5
Detailed information (abstract, keywords, etc)
Slides

1S-3 (Time: 10:28 - 10:32)
TitleImplementation of Double Arbiter PUF and Its Performance Evaluation on FPGA
Author*Takanori Machida (Univ. of Electro-Communications, Japan), Dai Yamamoto (Fujitsu Labs., Japan), Mitsugu Iwamoto, Kazuo Sakiyama (Univ. of Electro-Communications, Japan)
Pagepp. 6 - 7
Detailed information (abstract, keywords, etc)

1S-4 (Time: 10:32 - 10:36)
TitleA Negative-Resistance Sense Amplifier for Low-Voltage Operating STT-MRAM
Author*Yohei Umeki, Koji Yanagida (Kobe Univ., Japan), Shusuke Yoshimoto (Stanford Univ., U.S.A.), Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi (Kobe Univ., Japan), Koji Tsunoda, Toshihiro Sugii (Low-Power Electronics Association and Project (LEAP), Japan)
Pagepp. 8 - 9
Detailed information (abstract, keywords, etc)
Slides

1S-5 (Time: 10:36 - 10:40)
TitleA High Stability, Low Supply Voltage and Low Standby Power Six-Transistor CMOS SRAM
Author*Nobuaki Kobayashi, Ryusuke Ito, Tadayoshi Enomoto (Chuo Univ., Japan)
Pagepp. 10 - 11
Detailed information (abstract, keywords, etc)
Slides

1S-6 (Time: 10:40 - 10:44)
TitleAn Efficient Multi-Port Memory Controller for Multimedia Applications
Author*Xuan-Thuan Nguyen, Cong-Kha Pham (Univ. of Electro-Communications, Japan)
Pagepp. 12 - 13
Detailed information (abstract, keywords, etc)

1S-7 (Time: 10:44 - 10:48)
TitleReliability-Configurable Mixed-Grained Reconfigurable Array Compatible with High-Level Synthesis
Author*Masanori Hashimoto, Dawood Alnajjar, Hiroaki Konoura (Osaka Univ./JST, CREST, Japan), Yukio Mitsuyama (Kochi Univ. of Tech./JST, CREST, Japan), Hajime Shimada (Nagoya Univ./JST, CREST, Japan), Kazutoshi Kobayashi (Kyoto Inst. of Tech./JST, CREST, Japan), Hiroyuki Kanbara (ASTEM/JST, CREST, Japan), Hiroyuki Ochi (Ritsumeikan Univ./JST, CREST, Japan), Takashi Imagawa (Kyoto Univ./JST, CREST, Japan), Kazutoshi Wakabayashi (NEC/JST, CREST, Japan), Takao Onoye (Osaka Univ./JST, CREST, Japan), Hidetoshi Onodera (Kyoto Univ./JST, CREST, Japan)
Pagepp. 14 - 15
Detailed information (abstract, keywords, etc)
Slides

1S-8 (Time: 10:48 - 10:52)
TitleA 14μA ECG Processor with Noise Tolerant Heart Rate Extractor and FeRAM for Wearable Healthcare Systems
Author*Yozaburo Nakai, Shintaro Izumi, Ken Yamashita, Masanao Nakano, Hiroshi Kawaguchi, Masahiko Yoshimoto (Kobe Univ., Japan)
Pagepp. 16 - 17
Detailed information (abstract, keywords, etc)
Slides

1S-9 (Time: 10:52 - 10:56)
TitleA 128-Way FPGA Platform for the Acceleration of KLMS Algorithm
Author*Xiaowei Ren, Qihang Yu, Badong Chen, Nanning Zheng, Pengju Ren (Xi'an Jiaotong Univ., China)
Pagepp. 18 - 19
Detailed information (abstract, keywords, etc)
Slides

1S-10 (Time: 10:56 - 11:00)
TitleA Real-Time Permutation Entropy Computation for EEG Signals
Author*Xiaowei Ren, Qihang Yu, Badong Chen, Nanning Zheng, Pengju Ren (Xi'an Jiaotong Univ., China)
Pagepp. 20 - 21
Detailed information (abstract, keywords, etc)
Slides

1S-11 (Time: 11:00 - 11:04)
TitleA High Efficient Hardware Architecture for Multiview 3DTV
Author*Jiang Yu, Geng Liu, Xin Zhang, Pengju Ren (Xi'an Jiaotong Univ., China)
Pagepp. 22 - 23
Detailed information (abstract, keywords, etc)
Slides

1S-12 (Time: 11:04 - 11:08)
TitleDesign of A Scalable Many-Core Processor for Embedded Applications
Author*Hsiao-Wei Chien, Jyun-Long Lai, Chao-Chieh Wu, Chih-Tsun Huang, Ting-Shuo Hsu, Jing-Jia Liou (National Tsing Hua Univ., Taiwan)
Pagepp. 24 - 25
Detailed information (abstract, keywords, etc)

1S-13 (Time: 11:08 - 11:12)
TitleA DPA/DEMA/LEMA-Resistant AES Cryptographic Processor with Supply-Current Equalizer and Micro EM Probe Sensor
Author*Daisuke Fujimoto, Noriyuki Miura (Kobe Univ., Japan), Yu-ichi Hayashi, Naofumi Homma, Takafumi Aoki (Tohoku Univ., Japan), Makoto Nagata (Kobe Univ., Japan)
Pagepp. 26 - 27
Detailed information (abstract, keywords, etc)

1S-14 (Time: 11:12 - 11:16)
TitleA 64×64 1200fps Dual-Mode CMOS Ion-Image Sensor for Accurate DNA Sequencing
Author*Xiwei Huang, Jing Guo, Mei Yan, Hao Yu (Nanyang Technological Univ., Singapore)
Pagepp. 28 - 29
Detailed information (abstract, keywords, etc)
Slides

1S-16 (Time: 11:16 - 11:20)
TitleA 0.21-V Minimum Input, 73.6% Maximum Efficiency, Fully Integrated 3-Terminal Voltage Converter with MPPT for Low-Voltage Energy Harvesters
Author*Toshihiro Ozaki, Tetsuya Hirose, Takahiro Nagai, Keishi Tsubaki, Nobutaka Kuroki, Masahiro Numa (Kobe Univ., Japan)
Pagepp. 30 - 31
Detailed information (abstract, keywords, etc)
Slides

1S-17 (Time: 11:20 - 11:24)
TitleDual-Output Wireless Power Delivery System for Small Size Large Volume Wireless Memory Card
Author*Junki Hashiba, Toru Kawajiri, Yuya Hasegawa, Hiroki Ishikuro (Keio Univ., Japan)
Pagepp. 32 - 33
Detailed information (abstract, keywords, etc)
Slides

1S-18 (Time: 11:24 - 11:28)
TitleA Tri-Level 50MS/s 10-bit Capacitive-DAC for Bluetooth Applications
Author*Daisuke Kanemoto (Univ. of Yamanashi, Japan), Keigo Oshiro, Keiji Yoshida, Haruichi Kanaya (Kyushu Univ., Japan)
Pagepp. 34 - 35
Detailed information (abstract, keywords, etc)

1S-19 (Time: 11:28 - 11:32)
TitleA Tail-Current Modulated VCO with Adaptive-Bias Scheme
Author*Aravind Tharayil Narayanan, Wei Deng, Kenichi Okada, Akira Matsuzawa (Tokyo Inst. of Tech., Japan)
Pagepp. 36 - 37
Detailed information (abstract, keywords, etc)
Slides

1S-20 (Time: 11:32 - 11:36)
TitleA Low-Power VCO Based ADC with Asynchronous Sigma-Delta Modulator in 65nm CMOS
Author*Jili Zhang, Chenluan Wang, Shengxi Diao, Fujiang Lin (Univ. of Science and Tech. of China, China)
Pagepp. 38 - 39
Detailed information (abstract, keywords, etc)
Slides

1S-21 (Time: 11:36 - 11:40)
TitleA 0.5-V 5.8-GHz Low-Power Asymmetrical QPSK/OOK Transceiver for Wireless Sensor Network
Author*Sho Ikeda, Sang_yeop Lee, Shin Yonezawa, Yiming Fang, Motohiro Takayasu, Taisuke Hamada, Yosuke Ishikawa, Hiroyuki Ito, Noboru Ishihara, Kazuya Masu (Tokyo Inst. of Tech., Japan)
Pagepp. 40 - 41
Detailed information (abstract, keywords, etc)
Slides

1S-22 (Time: 11:40 - 11:44)
TitleA 58.3-to-65.4 GHz 34.2 mW Sub-Harmonically Injection-Locked PLL with a Sub-Sampling Phase Detection
Author*Teerachot Siriburanon, Tomohiro Ueno, Kento Kimura, Satoshi Kondo, Wei Deng, Kenichi Okada, Akira Matsuzawa (Tokyo Inst. of Tech., Japan)
Pagepp. 42 - 43
Detailed information (abstract, keywords, etc)

1S-23 (Time: 11:44 - 11:48)
TitleCircuit and Package Design for 44GB/s Inductive-Coupling DRAM/SoC Interface
Author*Akira Okada, Abdul Raziz Junaidi, Yasuhiro Take, Atsutake Kosuge, Tadahiro Kuroda (Keio Univ., Japan)
Pagepp. 44 - 45
Detailed information (abstract, keywords, etc)
Slides

1S-24 (Time: 11:48 - 11:52)
TitleDesign and Analysis for ThruChip Design for Manufacturing (DFM)
Author*Li-Chung Hsu, Yasuhiro Take, Atsutake Kosuge, So Hasegawa, Junichiro Kadamoto, Tadahiro Kuroda (Keio Univ., Japan)
Pagepp. 46 - 47
Detailed information (abstract, keywords, etc)
Slides


Session 1A  NoCS I (Performance and Fault Tolerance)
Time: 10:20 - 12:00 Tuesday, January 20, 2015
Location: Room 102
Chairs: Yoshinori Takeuchi (Osaka Univ., Japan), Takashi Miyamori (Toshiba)

1A-1 (Time: 10:20 - 10:45)
TitleA Novel Approach Using a Minimum Cost Maximum Flow Algorithm for Fault-Tolerant Topology Reconfiguration in NoC Architectures
AuthorLeibo Liu, *Yu Ren, Chenchen Deng (Tsinghua Univ., China), Jie Han (Univ. of Alberta, Canada), Shouyi Yin, Shaojun Wei (Tsinghua Univ., China)
Pagepp. 48 - 53
Detailed information (abstract, keywords, etc)
Slides

1A-2 (Time: 10:45 - 11:10)
TitleAdaptive Remaining Hop Count Flow Control: Consider the Interaction between Packets
Author*Peng Wang, Sheng Ma, Hongyi Lu, Zhiying Wang, Chen Li (National Univ. of Defense Tech., China)
Pagepp. 54 - 60
Detailed information (abstract, keywords, etc)
Slides

1A-3 (Time: 11:10 - 11:35)
TitleA Flexible Hardware Barrier Mechanism for Many-Core Processors
Author*Takeshi Soga (ISIT Kyushu, JST CREST, Japan), Hiroshi Sasaki, Tomoya Hirao (Kyushu Univ., Japan), Masaaki Kondo (Univ. of Tokyo, Japan), Koji Inoue (Kyushu Univ., Japan)
Pagepp. 61 - 68
Detailed information (abstract, keywords, etc)
Slides

1A-4 (Time: 11:35 - 12:00)
TitleA Performance Enhanced Dual-Switch Network-on-Chip Architecture
Author*Lian Zeng, Takahiro Watanabe (Waseda Univ., Japan)
Pagepp. 69 - 74
Detailed information (abstract, keywords, etc)
Slides


Session 1B  Toward Power Efficient Design
Time: 10:20 - 12:00 Tuesday, January 20, 2015
Location: Room 104
Chairs: Kimiyoshi Usami (Shibaura Inst. of Tech., Japan), Masanori Hashimoto (Osaka Univ., Japan)

1B-1 (Time: 10:20 - 10:45)
TitleA Cross-Layer Framework for Designing and Optimizing Deeply-Scaled FinFET-Based SRAM Cells under Process Variations
Author*Alireza Shafaei, Shuang Chen, Yanzhi Wang, Massoud Pedram (Univ. of Southern California, U.S.A.)
Pagepp. 75 - 80
Detailed information (abstract, keywords, etc)
Slides

1B-2 (Time: 10:45 - 11:10)
TitleControlled Placement of Standard Cell Memory Arrays for High Density and Low Power in 28nm FD-SOI
Author*Adam Teman (EPFL, Switzerland), Davide Rossi (Univ. of Bologna, Italy), Pascal Meinerzhagen (EPFL, Switzerland), Luca Benini (Univ. of Bologna, Italy/ETH, Switzerland), Andreas Burg (EPFL, Switzerland)
Pagepp. 81 - 86
Detailed information (abstract, keywords, etc)
Slides

1B-3 (Time: 11:10 - 11:35)
TitleMicroarchitectural-Level Statistical Timing Models for Near-Threshold Circuit Design
Author*Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera (Kyoto Univ., Japan)
Pagepp. 87 - 93
Detailed information (abstract, keywords, etc)

1B-4 (Time: 11:35 - 12:00)
TitleStress-Aware P/G TSV Planning in 3D-ICs
Author*Shengcheng Wang, Farshad Firouzi, Fabian Oboril, Mehdi B. Tahoori (Karlsruhe Inst. of Tech., Germany)
Pagepp. 94 - 99
Detailed information (abstract, keywords, etc)
Slides


Session 1C  Modeling and Design Methodologies of Post-silicon Devices
Time: 10:20 - 12:00 Tuesday, January 20, 2015
Location: Room 105
Chairs: Zili Shao (Hong Kong Polytechnic Univ., Hong Kong), Duo Liu (Chongqing Univ., China)

1C-1 (Time: 10:20 - 10:45)
TitleQuantitative Modeling of Racetrack Memory, A Tradeoff among Area, Performance, and Power
Author*Chao Zhang, Guangyu Sun, Weiqi Zhang (Peking Univ., China), Fan Mi, Hai Li (Univ. of Pittsburgh, U.S.A.), Weisheng Zhao (Beihang Univ., China)
Pagepp. 100 - 105
Detailed information (abstract, keywords, etc)
Slides

1C-2 (Time: 10:45 - 11:10)
TitleTechnological Exploration of RRAM Crossbar Array for Matrix-Vector Multiplication
Author*Peng Gu, Boxun Li, Tianqi Tang (Tsinghua Univ., China), Shimeng Yu, Yu Cao (Arizona State Univ., U.S.A.), Yu Wang, Huazhong Yang (Tsinghua Univ., China)
Pagepp. 106 - 111
Detailed information (abstract, keywords, etc)

1C-3 (Time: 11:10 - 11:35)
TitleModeling Framework for Cross-Point Resistive Memory Design Emphasizing Reliability and Variability Issues
AuthorYang Zheng, Cong Xu (Pennsylvania State Univ., U.S.A.), *Yuan Xie (Pennsylvania State Univ./Univ. of California, Santa Barbara, U.S.A.)
Pagepp. 112 - 117
Detailed information (abstract, keywords, etc)

1C-4 (Time: 11:35 - 12:00)
TitleA Defect-Aware Approach for Mapping Reconfigurable Single-Electron Transistor Arrays
Author*Ching-Yi Huang, Chian-Wei Liu, Chun-Yao Wang (National Tsing Hua Univ., Taiwan), Yung-Chih Chen (Yuan Ze Univ., Taiwan), Suman Datta, Vijaykrishnan Narayanan (Pennsylvania State Univ., U.S.A.)
Pagepp. 118 - 123
Detailed information (abstract, keywords, etc)
Slides


Session 2S  (Special Session) Internet of Things
Time: 13:50 - 15:30 Tuesday, January 20, 2015
Location: Room 103
Chair: Li Shang (Univ. of Colorado Boulder, U.S.A.)

2S-1 (Time: 13:50 - 14:20)
Title(Invited Paper) Powering the IoT: Storage-Less and Converter-Less Energy Harvesting
Author*Hyung Gyu Lee (Daegu Univ., Republic of Korea), Naehyuck Chang (KAIST, Republic of Korea)
Pagepp. 124 - 129
Detailed information (abstract, keywords, etc)

2S-2 (Time: 14:20 - 14:50)
Title(Invited Paper) Distributed Computing in IoT: System-on-a-Chip for Smart Cameras as an Example
Author*Shao-Yi Chien, Wei-Kai Chan, Yu-Hsiang Tseng (National Taiwan Univ., Taiwan), Chia-Han Lee (Academia Sinica, Taiwan), V. Srinivasa Somayazulu, Yen-Kuang Chen (Intel, U.S.A.)
Pagepp. 130 - 135
Detailed information (abstract, keywords, etc)

2S-3 (Time: 14:50 - 15:30)
Title(Invited Paper) Data Sensing and Analysis: Challenges for Wearables
AuthorJames Williamson, Qi Liu, Fenglong Lu, Wyatt Mohrman, Kun Li (Univ. of Colorado Boulder, U.S.A.), Robert P. Dick (Univ. of Michigan, U.S.A.), *Li Shang (Univ. of Colorado Boulder, U.S.A.)
Pagepp. 136 - 141
Detailed information (abstract, keywords, etc)


Session 2A  NoCS II (Power and Emerging Technology)
Time: 13:50 - 15:30 Tuesday, January 20, 2015
Location: Room 102
Chairs: Mehdi Tahoori (Karlsruhe Inst. of Tech., Germany), Tomoya Horiguchi (Toshiba)

2A-1 (Time: 13:50 - 14:15)
TitleShuttleNoC: Boosting On-Chip Communication Efficiency by Enabling Localized Power Adaptation
AuthorHang Lu (Univ. of Chinese Academy of Sciences, China), *Guihai Yan, Yinhe Han, Ying Wang (Chinese Academy of Sciences, China), Xiaowei Li (Univ. of Chinese Academy of Sciences, China)
Pagepp. 142 - 147
Detailed information (abstract, keywords, etc)

2A-2 (Time: 14:15 - 14:40)
TitleEnergy-Efficient Optical Crossbars on Chip with Multi-Layer Deposited Silicon
AuthorHui LI, *Sébastien Le Beux (Lyon Institute of Nanotechnology, France), Gabriela Nicolescu (Ecole Polytechnique de Montréal, Canada), Ian O'Connor (Lyon Institute of Nanotechnology, France)
Pagepp. 148 - 153
Detailed information (abstract, keywords, etc)

2A-3 (Time: 14:40 - 15:05)
TitleTwo-Phase Protocol Converters for 3D Asynchronous 1-of-n Data Links
AuthorJulian Hilgemberg Pontes, *Pascal Vivet, Yvain Thonnart (CEA/LETI, France)
Pagepp. 154 - 159
Detailed information (abstract, keywords, etc)
Slides

2A-4 (Time: 15:05 - 15:30)
TitleFine-Grained Runtime Power Budgeting for Networks-on-Chip
Author*Xiaohang Wang, Tengfei Wang (Chinese Academy of Sciences, China), Terrence Mak (Chinese Academy of Sciences/Chinese Univ. of Hong Kong, China), Mei Yang, Yingtao Jiang (Univ. of Nevada, Las Vegas, U.S.A.), Masoud Daneshtalab (Royal Inst. of Tech, Sweden/Univ. of Turku, Finland)
Pagepp. 160 - 165
Detailed information (abstract, keywords, etc)
Slides


Session 2B  Design Automation for Tomorrow’s Circuit Technologies
Time: 13:50 - 15:30 Tuesday, January 20, 2015
Location: Room 104
Chairs: Anupam Chattopadhyay (RWTH Aachen Univ., Germany), Shigeru Yamashita (Ritsumeikan Univ.)

2B-1 (Time: 13:50 - 14:15)
TitleNonvolatile Memory Allocation and Hierarchy Optimization for High-Level Synthesis
AuthorShuangchen Li (Tsinghua Univ., China/Univ. of California, Santa Barbara, U.S.A.), Ang Li, Yongpan Liu (Tsinghua Univ., China), *Yuan Xie (Univ. of California, Santa Barbara, U.S.A.), Huazhong Yang (Tsinghua Univ., China)
Pagepp. 166 - 171
Detailed information (abstract, keywords, etc)

2B-2 (Time: 14:15 - 14:40)
TitleReverse BDD-Based Synthesis for Splitter-Free Optical Circuits
AuthorRobert Wille, *Oliver Keszocze, Clemens Hopfmuller, Rolf Drechsler (Univ. of Bremen, Germany)
Pagepp. 172 - 177
Detailed information (abstract, keywords, etc)
Slides

2B-3 (Time: 14:40 - 15:05)
TitleDetermining the Minimal Number of SWAP Gates for Multi-Dimensional Nearest Neighbor Quantum Circuits
AuthorAaron Lye (Univ. of Bremen, Germany), *Robert Wille, Rolf Drechsler (Univ. of Bremen/Cyber Physical Systems, DFKI GmbH, Germany)
Pagepp. 178 - 183
Detailed information (abstract, keywords, etc)
Slides


Session 2C  Emerging Applications
Time: 13:50 - 15:30 Tuesday, January 20, 2015
Location: Room 105
Chairs: Juinn-Dar Huang (National Chiao Tung Univ., Taiwan), Youhua Shi (Waseda Univ.)

2C-1 (Time: 13:50 - 14:15)
TitleDesign and Optimization of 3D Digital Microfluidic Biochips for the Polymerase Chain Reaction
AuthorZipeng Li (Duke Univ., U.S.A.), Tsung-Yi Ho (National Chiao Tung Univ., Taiwan), *Krishnendu Chakrabarty (Duke Univ., U.S.A.)
Pagepp. 184 - 189
Detailed information (abstract, keywords, etc)
Slides

2C-2 (Time: 14:15 - 14:40)
TitleAn Accurate and Low Cost PM2.5 Estimation Method Based on Artificial Neural Network
Author*Lixue Xia, Rong Luo, Bin Zhao, Yu Wang, Huazhong Yang (Tsinghua Univ., China)
Pagepp. 190 - 195
Detailed information (abstract, keywords, etc)
Slides

2C-3 (Time: 14:40 - 15:05)
TitleIterative Disparity Voting Based Stereo Matching Algorithm and Its Hardware Implementation
AuthorZhi Hu, *Yibo Fan, Xiaoyang Zeng (Fudan Univ., China)
Pagepp. 196 - 201
Detailed information (abstract, keywords, etc)
Slides

2C-4 (Time: 15:05 - 15:30)
TitleObstacle-Avoiding Wind Turbine Placement for Power-Loss and Wake-Effect Optimization
Author*Yu-Wei Wu (National Cheng Kung Univ., Taiwan), Yi-yu Shi (Missouri Univ. of Science and Tech., U.S.A.), Sudip Roy (National Cheng Kung Univ., Taiwan), Tsung-Yi Ho (National Chiao Tung Univ., Taiwan)
Pagepp. 202 - 207
Detailed information (abstract, keywords, etc)
Slides


Session 3S  (Special Session) New Challenges and Solutions in Nanometer Physical Design
Time: 15:50 - 17:30 Tuesday, January 20, 2015
Location: Room 103
Chair: Mark Po-Hung Lin (National Chung Cheng Univ., Taiwan)

3S-1 (Time: 15:50 - 16:15)
Title(Invited Paper) An Efficient Linear Time Triple Patterning Solver
AuthorHaitong Tian (Univ. of Illinois, Urbana-Champaign, U.S.A.), Hongbo Zhang (Synopsys, U.S.A.), Zigang Xiao, *Martin D. F. Wong (Univ. of Illinois, Urbana-Champaign, U.S.A.)
Pagepp. 208 - 213
Detailed information (abstract, keywords, etc)

3S-2 (Time: 16:15 - 16:40)
Title(Invited Paper) Gate Sizing and Threshold Voltage Assignment for High Performance Microprocessor Designs
AuthorTiago Reimann (Univ. Federal do Rio Grande do Sul, Brazil), Cliff C.N. Sze (IBM, U.S.A.), *Ricardo Reis (Univ. Federal do Rio Grande do Sul, Brazil)
Pagepp. 214 - 219
Detailed information (abstract, keywords, etc)
Slides

3S-3 (Time: 16:40 - 17:05)
Title(Invited Paper) Analytical Placement for Rectilinear Blocks
Author*Yasuhiro Takashima (Univ. of Kitakyushu, Japan)
Pagepp. 220 - 225
Detailed information (abstract, keywords, etc)
Slides

3S-4 (Time: 17:05 - 17:30)
Title(Invited Paper) IR to Routing Challenge and Solution for Interposer-Based Design
Author*Eric Jia-Wei Fang, Terry Chi-Jih Shih, Darton Shen-Yu Huang (MediaTek, Taiwan)
Pagepp. 226 - 230
Detailed information (abstract, keywords, etc)


Session 3A  Circuits for Performance and Reliability
Time: 15:50 - 16:40 Tuesday, January 20, 2015
Location: Room 102
Chairs: Sri Parameswaran (Univ. of New South Wales, Australia), Chengmo Yang (Univ. of Delaware)

3A-1 (Time: 15:50 - 16:15)
TitleAging Mitigation in Memory Arrays Using Self-Controlled Bit-Flipping Technique
Author*Anteneh Gebregiorgis (TU Delft, Netherlands), Mojtaba Ebrahimi, Saman Kiamehr, Fabian Oboril (Karlsruhe Inst. of Tech., Germany), Said Hamdioui (TU Delft, Netherlands), Mehdi Tahoori (Karlsruhe Inst. of Tech., Germany)
Pagepp. 231 - 236
Detailed information (abstract, keywords, etc)

3A-2 (Time: 16:15 - 16:40)
TitleDesign Methodology for Approximate Accumulator Based on Statistical Error Model
AuthorChang Liu, *Xinghua Yang, Fei Qiao, Qi Wei, Huazhong Yang (Tsinghua Univ., China)
Pagepp. 237 - 242
Detailed information (abstract, keywords, etc)
Slides


Session 3B  Frontiers in Logic Synthesis
Time: 15:50 - 17:30 Tuesday, January 20, 2015
Location: Room 104
Chairs: Robert Wille (Univ. of Bremen, Germany), Yuko Hara-Azumi (Tokyo Inst. of Tech.)

3B-1 (Time: 15:50 - 16:15)
TitleMultiple Independent Gate FETs: How Many Gates Do We Need?
Author*Luca Amaru (Integrated Systems Laboratory - EPFL, Switzerland), Gage Hills (Stanford Univ., U.S.A.), Pierre-Emmanuel Gaillardon (Integrated Systems Laboratory - EPFL, Switzerland), Subhasish Mitra (Stanford Univ., U.S.A.), Giovanni De Micheli (Integrated Systems Laboratory - EPFL, Switzerland)
Pagepp. 243 - 248
Detailed information (abstract, keywords, etc)
Slides

3B-2 (Time: 16:15 - 16:40)
TitlePolynomial Time Algorithm for Area and Power Efficient Adder Synthesis in High-Performance Designs
AuthorSubhendu Roy (Univ. of Texas, Austin, U.S.A.), Mihir Choudhury, Ruchir Puri (IBM, U.S.A.), *David Z Pan (Univ. of Texas, Austin, U.S.A.)
Pagepp. 249 - 254
Detailed information (abstract, keywords, etc)

3B-3 (Time: 16:40 - 17:05)
TitleAccelerating SAT-Based Boolean Matching for Heterogeneous FPGAs Using One-Hot Encoding and CEGAR Technique
Author*Yusuke Matsunaga (Kyushu Univ., Japan)
Pagepp. 255 - 260
Detailed information (abstract, keywords, etc)


Session 3C  Energy Optimization for Electric Vehicles and Smart Grids
Time: 15:50 - 17:30 Tuesday, January 20, 2015
Location: Room 105
Chairs: Hideki Takase (Kyoto Univ., Japan), Yongpan Liu (Tsinghua Univ., China)

3C-1 (Time: 15:50 - 16:15)
TitleNegotiation-Based Task Scheduling and Storage Control Algorithm to Minimize User’s Electric Bills under Dynamic Prices
AuthorJi Li, Yanzhi Wang, Xue Lin, Shahin Nazarian, *Massoud Pedram (USC, U.S.A.)
Pagepp. 261 - 266
Detailed information (abstract, keywords, etc)
Slides

3C-2 (Time: 16:15 - 16:40)
TitleMany-to-Many Active Cell Balancing Strategy Design
Author*Matthias Kauer, Swaminathan Narayanaswamy, Sebastian Steinhorst, Martin Lukasiewycz (TUM CREATE, Singapore), Samarjit Chakraborty (TU Munich, Germany)
Pagepp. 267 - 272
Detailed information (abstract, keywords, etc)

3C-3 (Time: 16:40 - 17:05)
TitleIntra-Vehicle Network Routing Algorithm for Wiring Weight and Wireless Transmit Power Minimization
Author*Ta-Yang Huang, Chia-Jui Chang (National Cheng Kung Univ., Taiwan), Chung-Wei Lin (Univ. of California, Berkeley, U.S.A.), Sudip Roy (National Cheng Kung Univ., Taiwan), Tsung-Yi Ho (National Chiao Tung Univ., Taiwan)
Pagepp. 273 - 278
Detailed information (abstract, keywords, etc)

3C-4 (Time: 17:05 - 17:30)
TitleAn Autonomous Decentralized Mechanism for Energy Interchanges with Accelerated Diffusion Based on MCMC
Author*Yusuke Sakumoto (Tokyo Metropolitan Univ., Japan), Ittetsu Taniguchi (Ritsumeikan Univ., Japan)
Pagepp. 279 - 284
Detailed information (abstract, keywords, etc)
Slides



Wednesday, January 21, 2015

Session 2K  Keynote II
Time: 9:00 - 9:50 Wednesday, January 21, 2015
Location: International Conference Room
Chair: Kunio Uchiyama (Hitachi)

2K-1 (Time: 9:00 - 9:50)
Title(Keynote Address) Programmable Network
Author*Atsushi Takahara (NTT, Japan)
Pagep. 285
Detailed information (abstract, keywords, etc)


Session 4S  (Special Session) Machine Learning in EDA: Promises and Challenges in Selected Applications
Time: 10:15 - 12:20 Wednesday, January 21, 2015
Location: Room 103
Chair: Li-C. Wang (Univ. of California, Santa Barbara, U.S.A.)

4S-1 (Time: 10:15 - 10:45)
Title(Invited Paper) Machine Learning and Pattern Matching in Physical Design
AuthorBei Yu, *David Z. Pan (Univ. of Texas, Austin, U.S.A.), Tetsuaki Matsunawa (Toshiba, Japan), Xuan Zeng (Fudan Univ., China)
Pagepp. 286 - 293
Detailed information (abstract, keywords, etc)

4S-2 (Time: 10:45 - 11:15)
Title(Invited Paper) Self-Learning and Adaptive Board-Level Functional Fault Diagnosis
AuthorFangming Ye, *Krishnendu Chakrabarty (Duke Univ., U.S.A.), Zhaobo Zhang, Xinli Gu (Huawei Technologies, U.S.A.)
Pagepp. 294 - 301
Detailed information (abstract, keywords, etc)

4S-3 (Time: 11:15 - 11:45)
Title(Invited Paper) Fast Statistical Analysis of Rare Failure Events for Memory Circuits in High-Dimensional Variation Space
AuthorShupeng Sun, *Xin Li (Carnegie Mellon Univ., U.S.A.)
Pagepp. 302 - 307
Detailed information (abstract, keywords, etc)
Slides

4S-4 (Time: 11:45 - 12:20)
Title(Invited Paper) Data Mining in Functional Test Content Optimization
Author*Li-C. Wang (Univ. of California, Santa Barbara, U.S.A.)
Pagepp. 308 - 315
Detailed information (abstract, keywords, etc)


Session 4A  Efficient NVM Management, from Register to Disk
Time: 10:15 - 12:20 Wednesday, January 21, 2015
Location: Room 102
Chairs: Kyoungwoo Lee (Yonsei Univ., Republic of Korea), Koji Nii (Renesas Electronics)

4A-1 (Time: 10:15 - 10:40)
TitleCheckpoint-Aware Instruction Scheduling for Nonvolatile Processor with Multiple Functional Units
AuthorMimi Xie, Chen Pan, *Jingtong Hu (Oklahoma State Univ., U.S.A.), Chengmo Yang (Univ. of Delaware, U.S.A.), Yiran Chen (Univ. of Pittsburgh, U.S.A.)
Pagepp. 316 - 321
Detailed information (abstract, keywords, etc)
Slides

4A-2 (Time: 10:40 - 11:05)
TitleBalloonfish: Utilizing Morphable Resistive Memory in Mobile Virtualization
AuthorLinbo Long, Duo Liu, *Xiao Zhu, Kan Zhong (Chongqing Univ., China), Zili Shao (Hong Kong Polytechnic Univ., Hong Kong), Edwin H.-M. Sha (Chongqing Univ., China)
Pagepp. 322 - 327
Detailed information (abstract, keywords, etc)

4A-3 (Time: 11:05 - 11:30)
TitleA Three-Stage-Write Scheme with Flip-Bit for PCM Main Memory
AuthorYanbin Li, *Xin Li, Lei Ju, Zhiping Jia (Shandong Univ., China)
Pagepp. 328 - 333
Detailed information (abstract, keywords, etc)
Slides

4A-4 (Time: 11:30 - 11:55)
TitleA Garbage Collection Aware Stripping Method for Solid-State Drives
Author*Min Huang (Harbin Inst. of Tech., China), Yi Wang (Shenzhen Univ./Hong Kong Polytechnic Univ., China), Zhaoqing Liu, Liyan Qiao (Harbin Inst. of Tech., China), Zili Shao (Hong Kong Polytechnic Univ., Hong Kong)
Pagepp. 334 - 339
Detailed information (abstract, keywords, etc)

4A-5 (Time: 11:55 - 12:20)
TitleUnified Non-Volatile Memory and NAND Flash Memory Architecture in Smartphones
Author*Renhai Chen (Hong Kong Polytechnic Univ., Hong Kong), Yi Wang (Shenzhen Univ., China), Jingtong Hu (Oklahoma State Univ., U.S.A.), Duo Liu (Chongqing Univ., China), Zili Shao (Hong Kong Polytechnic Univ., Hong Kong), Yong Guan (Capital Normal Univ., China)
Pagepp. 340 - 345
Detailed information (abstract, keywords, etc)


Session 4B  Robust Timing, and P/G Modeling and Design
Time: 10:15 - 12:20 Wednesday, January 21, 2015
Location: Room 104
Chairs: Ray Cheung (City Univ. of Hong Kong, Hong Kong), Fan Yang (Fudan Univ., China)

4B-1 (Time: 10:15 - 10:40)
TitleA Retargetable and Accurate Methodology for Logic-IP-Internal Electromigration Assessment
AuthorPalkesh Jain (Qualcomm India Pvt, India), *Sachin S. Sapatnekar (Univ. of Minnesota, U.S.A.), Jordi Cortadella (Univ. Politècnica de Catalunya, Spain)
Pagepp. 346 - 351
Detailed information (abstract, keywords, etc)

4B-2 (Time: 10:40 - 11:05)
TitleNew Electromigration Modeling and Analysis Considering Time-Varying Temperature and Current Densities
AuthorHai-Bao Chen, *Sheldon X.-D. Tan, Xin Huang (Univ. of California, Riverside, U.S.A.), Valeriy Sukharev (Mentor Graphics, U.S.A.)
Pagepp. 352 - 357
Detailed information (abstract, keywords, etc)

4B-3 (Time: 11:05 - 11:30)
TitleGenerating Circuit Current Constraints to Guarantee Power Grid Safety
Author*Zahi Moudallal, Farid N Najm (Univ. of Toronto, Canada)
Pagepp. 358 - 365
Detailed information (abstract, keywords, etc)
Slides

4B-4 (Time: 11:30 - 11:55)
TitleBEE: Predicting Realistic Worst Case and Stochastic Eye Diagrams by Accounting for Correlated Bitstreams and Coding Strategies
AuthorAadithya Karthik (UC Berkeley, U.S.A.), Sayak Ray (Princeton Univ., U.S.A.), *Jaijeet Roychowdhury (UC Berkeley, U.S.A.)
Pagepp. 366 - 371
Detailed information (abstract, keywords, etc)

4B-5 (Time: 11:55 - 12:20)
TitleA Fast Parallel Approach for Common Path Pessimism Removal
Author*Chung-Hao Tsai, Wai-Kei Mak (National Tsing Hua Univ., Taiwan)
Pagepp. 372 - 377
Detailed information (abstract, keywords, etc)


Session 4C  New Issues in Placement and Routing
Time: 10:15 - 12:20 Wednesday, January 21, 2015
Location: Room 105
Chairs: Shigetoshi Nakatake (Univ. of Kitakyushu, Japan), Yuzi Kanazawa (Fujitsu Labs.)

4C-1 (Time: 10:15 - 10:40)
TitleDetailed-Routing-Driven Analytical Standard-Cell Placement
Author*Chau-Chin Huang, Chien-Hsiung Chiou, Kai-Han Tseng, Yao-Wen Chang (National Taiwan Univ., Taiwan)
Pagepp. 378 - 383
Detailed information (abstract, keywords, etc)

4C-2 (Time: 10:40 - 11:05)
TitleAn Approach to Anchoring and Placing High Performance Custom Digital Designs
Author*Shih-Ying Liu (National Chiao Tung Univ./MediaTek, Taiwan), Tung-Chieh Chen (Synopsys, Taiwan), Hung-Ming Chen (National Chiao Tung Univ., Taiwan)
Pagepp. 384 - 389
Detailed information (abstract, keywords, etc)

4C-3 (Time: 11:05 - 11:30)
TitleNon-Stitch Triple Patterning-Aware Routing Based on Conflict Graph Pre-Coloring
Author*Po-Ya Hsu, Yao-Wen Chang (National Taiwan Univ., Taiwan)
Pagepp. 390 - 395
Detailed information (abstract, keywords, etc)
Slides

4C-4 (Time: 11:30 - 11:55)
TitleCut Mask Optimization with Wire Planning in Self-Aligned Multiple Patterning Full-Chip Routing
Author*Shao-Yun Fang (National Taiwan Univ. of Science and Tech., Taiwan)
Pagepp. 396 - 401
Detailed information (abstract, keywords, etc)
Slides

4C-5 (Time: 11:55 - 12:20)
TitleA Length Matching Routing Method for Disordered Pins in PCB Design
Author*Ran Zhang, Tieyuan Pan, Li Zhu, Takahiro Watanabe (Waseda Univ., Japan)
Pagepp. 402 - 407
Detailed information (abstract, keywords, etc)
Slides


Session 5S  (Designers' Forum ) Car Electronics
Time: 13:50 - 15:30 Wednesday, January 21, 2015
Location: Room 103
Organizer: Shinichi Shibahara (Renesas Electronics, Japan), Chair: Koji Inoue (Kyushu Univ., Japan)

5S-1 (Time: 13:50 - 14:20)
Title(Invited Paper) Systems Modeling for Additional Development in Automotive E/E Architecture
Author*Hidekazu Nishimura (Keio Univ., Japan)
Pagepp. 408 - 409
Detailed information (abstract, keywords, etc)

5S-2 (Time: 14:20 - 14:50)
Title(Invited Paper) Implementation and Evaluation of Image Recognition Algorithm for An Intelligent Vehicle using Heterogeneous Multi-Core SoC
Author*Nau Ozaki, Masato Uchiyama, Yasuki Tanabe, Shuichi Miyazaki, Takaaki Sawada, Takanori Tamai, Moriyasu Banno (Toshiba, Japan)
Pagepp. 410 - 415
Detailed information (abstract, keywords, etc)

5S-3 (Time: 14:50 - 15:20)
Title(Invited Paper) Trend in Power Devices for Electric and Hybrid Electric Vehicles
Author*Khalid Hussein, Akira Fujita, Katsumi Sato (Mitsubishi Electric, Japan)
Pagep. 416
Detailed information (abstract, keywords, etc)


Session 5A  Optimization and Exploration for Caches
Time: 13:50 - 15:30 Wednesday, January 21, 2015
Location: Room 102
Chairs: Hiroyuki Tomiyama (Ritsumeikan Univ., Japan), Lin Meng (Ritsumeikan Univ., Japan)

5A-1 (Time: 13:50 - 14:15)
TitleMultilane Racetrack Caches: Improving Efficiency Through Compression and Independent Shifting
Author*Haifeng Xu (Univ. of Pittsburgh, U.S.A.), Yong Li (VMware, U.S.A.), Rami Melhem, Alex K. Jones (Univ. of Pittsburgh, U.S.A.)
Pagepp. 417 - 422
Detailed information (abstract, keywords, etc)
Slides

5A-2 (Time: 14:15 - 14:40)
TitleManaging Hybrid On-Chip Scratchpad and Cache Memories for Multi-Tasking Embedded Systems
AuthorZimeng Zhou, *Lei Ju, Zhiping Jia, Xin Li (Shandong Univ., China)
Pagepp. 423 - 428
Detailed information (abstract, keywords, etc)
Slides

5A-3 (Time: 14:40 - 15:05)
TitleOptimizing Thread-to-Core Mapping on Manycore Platforms with Distributed Tag Directories
Author*Guantao Liu, Tim Schmidt, Rainer Doemer (Univ. of California, Irvine, U.S.A.), Ajit Dingankar, Desmond Kirkpatrick (Intel, U.S.A.)
Pagepp. 429 - 434
Detailed information (abstract, keywords, etc)
Slides

5A-4 (Time: 15:05 - 15:30)
TitleAccelerating Non-Volatile/Hybrid Processor Cache Design Space Exploration for Application Specific Embedded Systems
Author*Mohammad Shihabul Haque, Ang Li, Akash Kumar (National Univ. of Singapore, Singapore), Qingsong Wei (Data Storage Institute, Singapore)
Pagepp. 435 - 440
Detailed information (abstract, keywords, etc)


Session 5B  CAD for Analog/RF/Mixed-Signal Design
Time: 13:50 - 15:30 Wednesday, January 21, 2015
Location: Room 104
Chairs: Sheldon Tan (Univ. of California, Riverside, U.S.A.), Mark Po-Hung Lin (National Chung Cheng Univ., Taiwan)

5B-1 (Time: 13:50 - 14:15)
TitleAccurate Passivity-Enforced Macromodeling for RF Circuits via Iterative Zero/Pole Update Based on Measurement Data
AuthorYing-Chih Wang, Shihui Yin, Minhee Jun, *Xin Li, Lawrence T. Pileggi, Tamal Mukherjee, Rohit Negi (Carnegie Mellon Univ., U.S.A.)
Pagepp. 441 - 446
Detailed information (abstract, keywords, etc)
Slides

5B-2 (Time: 14:15 - 14:40)
TitlePhysical Verification Flow for Hierarchical Analog IC Design Constraints
Author*Volker Meyer zu Bexten, Markus Tristl (Infineon Technologies AG, Germany), Göran Jerke (Robert Bosch GmbH, Germany), Hartmut Marquardt (Mentor Graphics, Germany), Dina Medhat (Mentor Graphics, Egypt)
Pagepp. 447 - 453
Detailed information (abstract, keywords, etc)
Slides

5B-3 (Time: 14:40 - 15:05)
TitleAutomatic Design for Analog/RF Front-End System in 802.11ac Receiver
Author*Zhijian Pan, Chuan Qin, Zuochang Ye, Yan Wang (Tsinghua Univ., China)
Pagepp. 454 - 459
Detailed information (abstract, keywords, etc)

5B-4 (Time: 15:05 - 15:30)
TitleSIPredict: Efficient Post-Layout Waveform Prediction via System Identification
Author*Qicheng Huang, Xiao Li, Fan Yang, Xuan Zeng (Fudan Univ., China), Xin Li (Fudan Univ., China/Carnegie Mellon Univ., U.S.A.)
Pagepp. 460 - 465
Detailed information (abstract, keywords, etc)
Slides


Session 5C  Next-Generation Clock Network Synthesis
Time: 13:50 - 15:30 Wednesday, January 21, 2015
Location: Room 105
Chairs: Atsushi Takahashi (Tokyo Inst. of Tech.), David Z. Pan (Univ. of Texas, Austin, U.S.A.)

5C-1 (Time: 13:50 - 14:15)
TitleUseful Clock Skew Scheduling Using Adjustable Delay Buffers in Multi-Power Mode Designs
Author*Juyeon Kim, Taewhan Kim (Seoul National Univ., Republic of Korea)
Pagepp. 466 - 471
Detailed information (abstract, keywords, etc)
Slides

5C-2 (Time: 14:15 - 14:40)
TitleFast Clock Skew Scheduling Based on Sparse-Graph Algorithms
Author*Rickard Ewetz (Purdue Univ., U.S.A.), Shankarshana Janarthanan (NVIDIA, U.S.A.), Cheng-Kok Koh (Purdue Univ., U.S.A.)
Pagepp. 472 - 477
Detailed information (abstract, keywords, etc)
Slides

5C-3 (Time: 14:40 - 15:05)
TitleModeling and Optimization of Low Power Resonant Clock Mesh
Author*Wulong Liu (Tsinghua Univ., China), Guoqing Chen (Research Lab, Advanced Micro Devices, China), Yu Wang, Huazhong Yang (Tsinghua Univ., China)
Pagepp. 478 - 483
Detailed information (abstract, keywords, etc)
Slides

5C-4 (Time: 15:05 - 15:30)
TitleSynthesis of Resonant Clock Networks Supporting Dynamic Voltage / Frequency Scaling
Author*Seyong Ahn, Minseok Kang (Seoul National Univ., Republic of Korea), Marios C. Papaefthymiou (Univ. of Michigan, U.S.A.), Taewhan Kim (Seoul National Univ., Republic of Korea)
Pagepp. 484 - 489
Detailed information (abstract, keywords, etc)
Slides


Session 6S  (Designers' Forum) Panel Discussion: Challenges in the Era of Big-Data Computing
Time: 15:50 - 17:30 Wednesday, January 21, 2015
Location: Room 103
Organizer: Koji Inoue (Kyushu Univ., Japan), Moderator: Koichiro Yamashita (Fujitsu Labs., Japan)

6S-1 (Time: 15:50 - 17:30)
Title(Panel Discussion) Challenges in the Era of Big-Data Computing
AuthorPanelists: Kento Aida (NII, Japan), Derek Chiou (Microsoft, U.S.A.), Hiroshi Nakamura (Univ. of Tokyo, Japan), Hiroyuki Tanaka (Nippon Telegraph and Telephone, Japan), Iwao Yamazaki (Fujitsu, Japan)
Detailed information (abstract, keywords, etc)


Session 6A  Optimization Techniques for Non-Volatile Memory based Systems
Time: 15:50 - 17:30 Wednesday, January 21, 2015
Location: Room 102
Chairs: Guangyu Sun (Peking Univ., China), Ju Lei (Shandong Univ.)

6A-1 (Time: 15:50 - 16:15)
TitleAn Efficient STT-RAM-Based Register File in GPU Architectures
AuthorXiaoxiao Liu, Mengjie Mao, Xiuyuan Bi, Hai Li, *Yiran Chen (Univ. of Pittsburgh, U.S.A.)
Pagepp. 490 - 495
Detailed information (abstract, keywords, etc)
Slides

6A-2 (Time: 16:15 - 16:40)
TitleA Bit-Write Reduction Method based on Error-Correcting Codes for Non-Volatile Memories
Author*Masashi Tawada, Shinji Kimura, Masao Yanagisawa, Nozomu Togawa (Waseda Univ., Japan)
Pagepp. 496 - 501
Detailed information (abstract, keywords, etc)

6A-3 (Time: 16:40 - 17:05)
TitleMinimizing MLC PCM Write Energy for Free through Profiling-Based State Remapping
Author*Mengying Zhao (City Univ. of Hong Kong, Hong Kong), Yuan Xue, Chengmo Yang (Univ. of Delaware, U.S.A.), Chun Jason Xue (City Univ. of Hong Kong, Hong Kong)
Pagepp. 502 - 507
Detailed information (abstract, keywords, etc)
Slides

6A-4 (Time: 17:05 - 17:30)
TitleImproving Performance and Lifetime of DRAM-PCM Hybrid Main Memory through a Proactive Page Allocation Strategy
AuthorHoda Aghaei Khouzani, *Chengmo Yang (Univ. of Delaware, U.S.A.), Jingtong Hu (Oklahoma State Univ., U.S.A.)
Pagepp. 508 - 513
Detailed information (abstract, keywords, etc)


Session 6B  Test for Higher Quality
Time: 15:50 - 17:30 Wednesday, January 21, 2015
Location: Room 104
Chairs: Tomokazu Yoneda (NAIST, Japan), Stefan Holst (Kyushu Inst. of Tech.)

6B-1 (Time: 15:50 - 16:15)
TitleEnhanced LCCG: A Novel Test Clock Generation Scheme for Faster-than-at-Speed Delay Testing
Author*Songwei Pei, Ye Geng (Beijing Univ. of Chemical Tech., China), Huawei Li (Key Laboratory of Computer System and Architecture, Institute of Computing Technology, China), Jun Liu (Hefei Univ. of Tech., China), Song Jin (North China Electric Power Univ., China)
Pagepp. 514 - 519
Detailed information (abstract, keywords, etc)

6B-2 (Time: 16:15 - 16:40)
TitleAn Efficient 3D-IC On-Chip Test Framework to Embed TSV Testing in Memory BIST
AuthorLiang-Che Li, Wen-Hsuan Hsu, *Kuen-Jong Lee (National Cheng Kung Univ., Taiwan), Chun-Lung Hsu (ITRI, Taiwan)
Pagepp. 520 - 525
Detailed information (abstract, keywords, etc)

6B-3 (Time: 16:40 - 17:05)
TitleAn Integrated Temperature-Cycling Acceleration and Test Technique for 3D Stacked ICs
Author*Nima Aghaee, Zebo Peng, Petru Eles (Linköping Univ., Sweden)
Pagepp. 526 - 531
Detailed information (abstract, keywords, etc)
Slides

6B-4 (Time: 17:05 - 17:30)
TitleSoftware-Based Test and Diagnosis of SoCs Using Embedded and Wide-I/O DRAM
Author*Sergej Deutsch, Krishnendu Chakrabarty (Duke Univ., U.S.A.)
Pagepp. 532 - 537
Detailed information (abstract, keywords, etc)


Session 6C  Reliability
Time: 15:50 - 17:30 Wednesday, January 21, 2015
Location: Room 105
Chairs: Xuan Zeng (Fudan Univ., China), Martin Wong (UIUC, U.S.A.)

6C-1 (Time: 15:50 - 16:15)
TitleLogic-DRAM Co-Design to Efficiently Repair Stacked DRAM With Unused Spares
AuthorMinjie Lv, *Hongbin Sun, Jingmin Xin, Nanning Zheng (Xi'an Jiaotong Univ., China)
Pagepp. 538 - 543
Detailed information (abstract, keywords, etc)

6C-2 (Time: 16:15 - 16:40)
TitleElectromigration-Aware Redundant via Insertion
AuthorJiwoo Pak, Bei Yu, *David Z. Pan (Univ. of Texas, Austin, U.S.A.)
Pagepp. 544 - 549
Detailed information (abstract, keywords, etc)

6C-3 (Time: 16:40 - 17:05)
TitleSynthesis of Resilient Circuits from Guarded Atomic Actions
AuthorYuankai Chen (Synopsys, U.S.A.), *Hai Zhou (Northwestern Univ., U.S.A.)
Pagepp. 550 - 555
Detailed information (abstract, keywords, etc)

6C-4 (Time: 17:05 - 17:30)
TitleIncremental Latin Hypercube Sampling for Lifetime Stochastic Behavioral Modeling of Analog Circuits
AuthorYen-Lung Chen (National Central Univ., Taiwan), Wei Wu (Univ. of California, Los Angeles, U.S.A.), *Chien-Nan Jimmy Liu (National Central Univ., Taiwan), Lei He (Univ. of California, Los Angeles, U.S.A.)
Pagepp. 556 - 561
Detailed information (abstract, keywords, etc)
Slides



Thursday, January 22, 2015

Session 3K  Keynote III
Time: 9:00 - 9:50 Thursday, January 22, 2015
Location: International Conference Room
Chair: Kunio Uchiyama (Hitachi)

3K-1 (Time: 9:00 - 9:50)
Title(Keynote Address) When and How Will an AI Be Smart Enough to Design?
Author*Noriko Arai (NII, Japan)
Pagep. 562
Detailed information (abstract, keywords, etc)


Session 7S  (Special Session) The Future of Emerging ReRAM Technology
Time: 10:15 - 12:20 Thursday, January 22, 2015
Location: Room 103
Chairs: Guangyu Sun (Peking Univ., China), Yuan Xie (Univ. of California, Santa Barbara, U.S.A.)

7S-1 (Time: 10:15 - 10:45)
Title(Invited Paper) Toward Large-Scale Access-Transistor-Free Memristive Crossbars
AuthorAmirali Ghofrani, Miguel Angel Lastras-Montaño, *K.-T. Tim Cheng (Univ. of California, Santa Barbara, U.S.A.)
Pagepp. 563 - 568
Detailed information (abstract, keywords, etc)
Slides

7S-2 (Time: 10:45 - 11:15)
Title(Invited Paper) Read Circuits for Resistive Memory (ReRAM) and Memristor-Based Nonvolatile Logics
Author*Meng-Fan Chang, Albert Lee, Chien-Chen Lin (National Tsing Hua Univ., Taiwan), Mon-Shu Ho (National Chung Hsin Univ., Taiwan), Ping-Cheng Chen (I-Shou Univ., Taiwan), Chia-Chen Kuo, Ming-Pin Chen, Pei-Ling Tseng, Tzu-Kun Ku (ITRI, Taiwan), Chien-Fu Chen, Kai-Shin Li, Jia-Min Shieh (National Nano Device Laboratories, Taiwan)
Pagepp. 569 - 574
Detailed information (abstract, keywords, etc)

7S-3 (Time: 11:15 - 11:45)
Title(Invited Paper) 3D ReRAM with Field Assisted Super-Linear Threshold (FASTTM) Selector Technology for Super-Dense, Low Power, Low Latency Data Storage Systems
AuthorSung Hyun Jo, Tanmay Kumar, Mehdi Asnaashari, Wei D. Lu, *Hagop Nazarian (Crossbar, U.S.A.)
Pagep. 575
Detailed information (abstract, keywords, etc)

7S-4 (Time: 11:45 - 12:20)
Title(Invited Paper) Modeling and Design Optimization of ReRAM
Author*J. F. Kang, H. T. Li, P. Huang, Z. Chen, B. Gao, X. Y. Liu (Peking Univ., China), Z. Z. Jiang, H.-S. P. Wong (Stanford Univ., U.S.A.)
Pagepp. 576 - 581
Detailed information (abstract, keywords, etc)
Slides


Session 7A  Ensuring the Correctness of System Integration
Time: 10:15 - 12:20 Thursday, January 22, 2015
Location: Room 102
Chairs: Takeshi Matsumoto (Ishitawa National College of Tech.), Akash Kumar (Natioanl Univ. of Singapore, Singapore)

7A-1 (Time: 10:15 - 10:40)
TitleEvaluation of Runtime Monitoring Methods for Real-Time Event Streams
Author*Biao Hu, Kai Huang, Gang Chen, Alois Knoll (Technical Univ. of Muenchen, Germany)
Pagepp. 582 - 587
Detailed information (abstract, keywords, etc)
Slides

7A-2 (Time: 10:40 - 11:05)
TitleAutomatic Timing-Coherent Transactor Generation for Mixed-Level Simulations
Author*Li-chun Chen, Hsin-I Wu, Ren-Song Tsay (National Tsing Hua Univ., Taiwan)
Pagepp. 588 - 593
Detailed information (abstract, keywords, etc)
Slides

7A-3 (Time: 11:05 - 11:30)
TitleHybrid Coverage Assertions for Efficient Coverage Analysis Across Simulation and Emulation Environments
AuthorHsuan-Ming Chou, Hong-Chang Wu, Yi-Chiao Chen, *Jean Tsao, Shih-Chieh Chang (National Tsing Hua Univ., Taiwan)
Pagepp. 594 - 599
Detailed information (abstract, keywords, etc)
Slides

7A-4 (Time: 11:30 - 11:55)
TitleSWAT: Assertion-Based Debugging of Concurrency Issues at System Level
Author*Luis Gabriel Murillo, Róbert Lajos Bücs, Daniel Hincapie, Rainer Leupers, Gerd Ascheid (RWTH Aachen Univ., Germany)
Pagepp. 600 - 605
Detailed information (abstract, keywords, etc)

7A-5 (Time: 11:55 - 12:20)
TitleCommunication Protocol Analysis of Transaction-Level Models Using Satisfiability Modulo Theories
Author*Che-Wei Chang, Rainer Doemer (Univ. of California, Irvine, U.S.A.)
Pagepp. 606 - 611
Detailed information (abstract, keywords, etc)
Slides


Session 7B  Orchestrating Tasks, Cores, and Communication
Time: 10:15 - 12:20 Thursday, January 22, 2015
Location: Room 104
Chairs: Zili Shao (Hong Kong Polytechnic Univ., Hong Kong), Masanori Hashimoto (Osaka Univ., Japan)

7B-1 (Time: 10:15 - 10:40)
TitleGuiding Fault-Driven Adaption in Multicore Systems through a Reliability-Aware Static Task Schedule
AuthorLaura A Rozo Duque, *Chengmo Yang (Univ. of Delaware, U.S.A.)
Pagepp. 612 - 617
Detailed information (abstract, keywords, etc)

7B-2 (Time: 10:40 - 11:05)
TitleApproximation-Aware Scheduling on Heterogeneous Multi-Core Architectures
Author*Cheng Tan, Thannirmalai Somu Muthukaruppan, Tulika Mitra (National Univ. of Singapore, Singapore), Lei Ju (Shandong Univ., China)
Pagepp. 618 - 623
Detailed information (abstract, keywords, etc)
Slides

7B-3 (Time: 11:05 - 11:30)
TitleComposing Real-Time Applications from Communicating Black-Box Components
Author*Martin Becker (Tech. Univ. of Munich, Germany), Alejandro Masrur (Software Technology for Embedded Systems, Technical Univ. Chemnitz, Germany), Samarjit Chakraborty (Tech. Univ. of Munich, Germany)
Pagepp. 624 - 629
Detailed information (abstract, keywords, etc)
Slides

7B-4 (Time: 11:30 - 11:55)
TitleEnhanced Partitioned Scheduling of Mixed-Criticality Systems on Multicore Platforms
Author*Zaid Al-bayati (McGill Univ., Canada), Qingling Zhao (Zhejiang Univ., China), Ahmed Youssef (McGill Univ., Canada), Haibo Zeng (Virginia Tech, U.S.A.), Zonghua Gu (Zhejiang Univ., China)
Pagepp. 630 - 635
Detailed information (abstract, keywords, etc)

7B-5 (Time: 11:55 - 12:20)
TitleReducing Dynamic Dispatch Overhead (DDO) of SLDL-Synthesized Embedded Software
AuthorJiaxing Zhang, Sanyuan Tang, *Gunar Schirner (Northeastern Univ., U.S.A.)
Pagepp. 636 - 643
Detailed information (abstract, keywords, etc)


Session 7C  Design for Manufacturability
Time: 10:15 - 12:20 Thursday, January 22, 2015
Location: Room 105
Chairs: Shigeki Nojima (Toshiba, Japan), Eric J.-W. Fang (MediaTek, Taiwan)

7C-1 (Time: 10:15 - 10:40)
TitleContact Pitch and Location Prediction for Directed Self-Assembly Template Verification
AuthorZigang Xiao, Yuelin Du, *Martin D.F. Wong (Univ. of Illinois, Urbana-Champaign, U.S.A.), He Yi, H.-S. Philip Wong (Stanford Univ., U.S.A.), Hongbo Zhang (Synopsys, U.S.A.)
Pagepp. 644 - 651
Detailed information (abstract, keywords, etc)
Slides

7C-2 (Time: 10:40 - 11:05)
TitleLayout Decomposition Co-Optimization for Hybrid E-Beam and Multiple Patterning Lithography
Author*Yunfeng Yang, Wai-Shing Luk (Fudan Univ., China), Hai Zhou (Fudan Univ., China/Northwestern Univ., U.S.A.), Changhao Yan, Xuan Zeng (Fudan Univ., China), Dian Zhou (Fudan Univ, China/Univ. of Texas, Dallas, U.S.A.)
Pagepp. 652 - 657
Detailed information (abstract, keywords, etc)

7C-3 (Time: 11:05 - 11:30)
TitlePolynomial Time Optimal Algorithm for Stencil Row Planning in E-Beam Lithography
AuthorDaifeng Guo, Yuelin Du, *Martin D.F. Wong (Univ. of Illinois, Urbana-Champaign, U.S.A.)
Pagepp. 658 - 664
Detailed information (abstract, keywords, etc)

7C-4 (Time: 11:30 - 11:55)
TitleFast Mask Assignment Using Positive Semidefinite Relaxation in LELECUT Triple Patterning Lithography
Author*Yukihide Kohira (Univ. of Aizu, Japan), Tomomi Matsui (Tokyo Inst. of Tech., Japan), Yoko Yokoyama, Chikaaki Kodama (Toshiba, Japan), Atsushi Takahashi (Tokyo Inst. of Tech., Japan), Shigeki Nojima, Satoshi Tanaka (Toshiba, Japan)
Pagepp. 665 - 670
Detailed information (abstract, keywords, etc)

7C-5 (Time: 11:55 - 12:20)
TitleLayout Decomposition for Spacer-is-Metal (SIM) Self-Aligned Double Patterning
Author*Shao-Yun Fang (National Taiwan Univ. of Science and Tech., Taiwan), Yi-Shu Tai, Yao-Wen Chang (National Taiwan Univ., Taiwan)
Pagepp. 671 - 676
Detailed information (abstract, keywords, etc)
Slides


Session 8S  (Designers' Forum) Technology Trend toward 8K Era
Time: 13:50 - 15:30 Thursday, January 22, 2015
Location: Room 103
Organizer: Hiroe Iwasaki (NTT, Japan), Chair: Masaitsu Nakajima (Panasonic, Japan)

8S-1 (Time: 13:50 - 14:15)
Title(Invited Paper) The Prospects of Next Generation Television - Japan’s Initiative to 2020 -
Author*Keiya Motohashi (NetTV Forum, Japan)
Pagepp. 677 - 679
Detailed information (abstract, keywords, etc)

8S-2 (Time: 14:15 - 14:40)
Title(Invited Paper) 8K LCD : Technologies and Challenges toward the Realization of SUPER Hi-VISION TV
Author*Takeshi Kumakura (SHARP, Japan)
Pagepp. 680 - 683
Detailed information (abstract, keywords, etc)

8S-3 (Time: 14:40 - 15:05)
Title(Invited Paper) The World's 1st Complete-4K SoC Solution with Hybrid Memory System
Author*Daisuke Murakami, Yuki Soga, Daisuke Imoto, Yoshiharu Watanabe, Takashi Yamada (Panasonic, Japan)
Pagepp. 684 - 686
Detailed information (abstract, keywords, etc)

8S-4 (Time: 15:05 - 15:30)
Title(Invited Paper) H.265/HEVC Encoder for UHDTV
Author*Mitsuo Ikeda (NTT, Japan)
Pagepp. 687 - 688
Detailed information (abstract, keywords, etc)


Session 8A  Exploring Better Architecture of Your Systems
Time: 13:50 - 15:30 Thursday, January 22, 2015
Location: Room 102
Chairs: Rainer Doemer (Univ. of California, Irvine, U.S.A.), Hoeseok Yang (Ajou Univ., Republic of Korea)

8A-1 (Time: 13:50 - 14:15)
TitleAn Accurate ACOSSO Metamodeling Technique for Processor Architecture Design Space Exploration
Author*Hongwei Wang (Beijing Key Laboratory of Mobile Computing and Pervasive Device/Chinese Academy of Sciences/Univ. of Chinese Academy of Sciences, China), Ziyuan Zhu, Jinglin Shi, Yongtao Su (Beijing Key Laboratory of Mobile Computing and Pervasive Device/Chinese Academy of Sciences, China)
Pagepp. 689 - 694
Detailed information (abstract, keywords, etc)

8A-2 (Time: 14:15 - 14:40)
TitleSpeeding Up Single Pass Simulation of PLRUt Caches
Author*Josef Schneider, Jorgen Peddersen, Sri Parameswaran (Univ. of New South Wales, Australia)
Pagepp. 695 - 700
Detailed information (abstract, keywords, etc)
Slides

8A-3 (Time: 14:40 - 15:05)
TitleADAPT: An ADAptive Manycore Methodology for Software Pipelined ApplicaTions
Author*Xi Zhang, Haris Javaid (Univ. of New South Wales, Australia), Muhammad Shafique (Karlsruhe Inst. of Tech., Germany), Jude Angelo Ambrose (Univ. of New South Wales, Australia), Jörg Henkel (Karlsruhe Inst. of Tech., Germany), Sri Parameswaran (Univ. of New South Wales, Australia)
Pagepp. 701 - 706
Detailed information (abstract, keywords, etc)
Slides

8A-4 (Time: 15:05 - 15:30)
TitleA Trace-Driven Approach for Fast and Accurate Simulation of Manycore Architectures
Author*Anastasiia Butko, Rafael Garibotti, Luciano Ost, Vianney Lapotre, Abdoulaye Gamatie, Gilles Sassatelli (LIRMM/CNRS/Univ. of Montpellier II, France), Chris Adeniyi-Jones (ARM, U.K.)
Pagepp. 707 - 712
Detailed information (abstract, keywords, etc)
Slides


Session 8B  Circuit-Level Modeling and Simulation
Time: 13:50 - 15:30 Thursday, January 22, 2015
Location: Room 104
Chairs: Luca Daniel (Massachusetts Inst. of Tech., U.S.A.), Takashi Sato (Kyoto Univ.)

8B-1 (Time: 13:50 - 14:15)
TitleCompact Modeling of Microbatteries Using Behavioral Linearization and Model-Order Reduction
AuthorMohammed Shemsu Nesro (Masdar Inst. of Tech., United Arab Emirates), Lizhong Sun (Applied Materials, U.S.A.), *Ibrahim (Abe) M. Elfadel (Masdar Inst. of Science and Tech., United Arab Emirates)
Pagepp. 713 - 718
Detailed information (abstract, keywords, etc)

8B-2 (Time: 14:15 - 14:40)
TitleGPU-Accelerated Parallel Monte Carlo Analysis of Analog Circuits by Hierarchical Graph-Based Solver
AuthorYan Zhu, *Sheldon X.-D. Tan (Univ. of California, Riverside, U.S.A.)
Pagepp. 719 - 724
Detailed information (abstract, keywords, etc)

8B-3 (Time: 14:40 - 15:05)
TitleAutomated Generation of Hybrid System Models for Reachability Analysis of Nonlinear Analog Circuits
Author*Hyun-Sek Lukas Lee (Leibniz Univ. Hannover, Germany), Matthias Althoff (Tech. Univ. München, Germany), Stefan Hoelldampf, Markus Olbrich, Erich Barke (Leibniz Univ. Hannover, Germany)
Pagepp. 725 - 730
Detailed information (abstract, keywords, etc)

8B-4 (Time: 15:05 - 15:30)
TitleArea Efficient Device-Parameter Estimation Using Sensitivity-Configurable Ring Oscillator
Author*Shoichi Iizuka, Yuma Higuchi, Masanori Hashimoto, Takao Onoye (Osaka Univ., Japan)
Pagepp. 731 - 736
Detailed information (abstract, keywords, etc)
Slides


Session 8C  Reliable and Trustworthy Electronics
Time: 13:50 - 15:30 Thursday, January 22, 2015
Location: Room 105
Chairs: Takashi Aikyo (STARC, Japan), Eishi Ibe (Hitachi)

8C-1 (Time: 13:50 - 14:15)
TitleOn Test Syndrome Merging for Reasoning-Based Board-Level Functional Fault Diagnosis
AuthorZelong Sun (Chinese Univ. of Hong Kong, Hong Kong), *Li Jiang (Shanghai Jiao Tong Univ., China), Qiang Xu (Chinese Univ. of Hong Kong, Hong Kong), Zhaobo Zhang, Zhiyuan Wang, Xinli Gu (Huawei Technologies, U.S.A.)
Pagepp. 737 - 742
Detailed information (abstract, keywords, etc)
Slides

8C-2 (Time: 14:15 - 14:40)
TitleEvent-Driven Transient Error Propagation: A Scalable and Accurate Soft Error Rate Estimation Approach
AuthorMojtaba Ebrahimi, Razi Seyyedi, Liang Chen, *Mehdi Tahoori (Karlsruhe Inst. of Tech., Germany)
Pagepp. 743 - 748
Detailed information (abstract, keywords, etc)

8C-3 (Time: 14:40 - 15:05)
TitleA Novel Methodology for Testing Hardware Security and Trust Exploiting On-Chip Power Noise Measurement
Author*Daisuke Fujimoto, Makoto Nagata (Kobe Univ., Japan), Shivam Bhasin, Jean-Luc Danger (Telecom Paristech, France)
Pagepp. 749 - 754
Detailed information (abstract, keywords, etc)

8C-4 (Time: 15:05 - 15:30)
TitleHardware Trojan Detection Using Exhaustive Testing of k-bit Subspaces
AuthorNicole Lesperance, Shrikant Kulkarni, *Kwang-Ting Cheng (UC Santa Barbara, U.S.A.)
Pagepp. 755 - 760
Detailed information (abstract, keywords, etc)
Slides


Session 9S  (Designers' Forum) Panel Discussion: IP Base SoC Design and IP Design Innovation
Time: 15:50 - 17:30 Thursday, January 22, 2015
Location: Room 103
Organizer: Nobuyuki Nishiguchi (Cadence Design Systems, Japan), Moderator: Toshihiro Hattori (Renesas System Design, Japan)

9S-1 (Time: 15:50 - 17:30)
Title(Panel Discussion) IP Base SoC Design and IP Design Innovation
AuthorPanelists: Hironori Ando (Synopsys, Japan), Kevin Yee (Cadence, U.S.A.), Randy Smith (Sonics, U.S.A.), Neil Parris (ARM, U.K.)
Detailed information (abstract, keywords, etc)


Session 9A  Power/Thermal Management and Modeling
Time: 15:50 - 17:30 Thursday, January 22, 2015
Location: Room 102
Chairs: Donghwa Shin (Yeungnam Univ., Republic of Korea), Takashi Nakada (Univ. of Tokyo, Japan)

9A-1 (Time: 15:50 - 16:15)
TitleAROMA: A Highly Accurate Microcomponent-Based Approach for Embedded Processor Power Analysis
AuthorZih-Ci Huang, *Chi-Kang Chen, Ren-Song Tsay (National Tsing Hua Univ., Taiwan)
Pagepp. 761 - 766
Detailed information (abstract, keywords, etc)
Slides

9A-2 (Time: 16:15 - 16:40)
TitleBattery-Aware Mapping Optimization of Loop Nests for CGRAs
Author*Yu Peng, Shouyi Yin, Leibo Liu, Shaojun Wei (Tsinghua Univ., China)
Pagepp. 767 - 772
Detailed information (abstract, keywords, etc)
Slides

9A-3 (Time: 16:40 - 17:05)
TitleTHOR: Orchestrated Thermal Management of Cores and Networks in 3D Many-Core Architectures
Author*Jinho Lee, Junwhan Ahn, Kiyoung Choi (Seoul National Univ., Republic of Korea), Kyungsu Kang (Samsung Electronics, Republic of Korea)
Pagepp. 773 - 778
Detailed information (abstract, keywords, etc)
Slides

9A-4 (Time: 17:05 - 17:30)
TitleEarly Stage Real-Time SoC Power Estimation Using RTL Instrumentation
AuthorJianlei Yang (Tsinghua Univ./Intel, China), *Liwei Ma, Kang Zhao (Intel, China), Yici Cai (Tsinghua Univ., China), Tin-Fook Ngai (Intel, China)
Pagepp. 779 - 784
Detailed information (abstract, keywords, etc)
Slides


Session 9B  (Special Session) System-Level Designs and Tools for Multicore Systems
Time: 15:50 - 17:30 Thursday, January 22, 2015
Location: Room 104
Chair: Chung-Ta King (National Tsing Hua Univ., Taiwan)

9B-1 (Time: 15:50 - 16:15)
Title(Invited Paper) Heterogeneous Architecture Design with Emerging 3D and Non-Volatile Memory Technologies
AuthorQiaosha Zou, Matthew Poremba (Pennsylvania State Univ., U.S.A.), Rui He, Wei Yang, Junfeng Zhao (Huawei Shannon Lab, China), *Yuan Xie (Univ. of California, Santa Barbara, U.S.A.)
Pagepp. 785 - 790
Detailed information (abstract, keywords, etc)

9B-2 (Time: 16:15 - 16:40)
Title(Invited Paper) Alleviate Chip I/O Pin Constraints for Multicore Processors through Optical Interconnects
Author*Zhehui Wang, Jiang Xu, Peng Yang, Xuan Wang, Zhe Wang, Luan H.K. Duong, Zhifei Wang, Haoran Li, Rafael K.V. Maeda, Xiaowen Wu (Hong Kong Univ. of Science and Tech., Hong Kong), Yaoyao Ye, Qinfen Hao (Huawei Technologies, China)
Pagepp. 791 - 796
Detailed information (abstract, keywords, etc)
Slides

9B-3 (Time: 16:40 - 17:05)
Title(Invited Paper) A Fast and Accurate Network-on-Chip Timing Simulator with a Flit Propagation Model
AuthorTing-Shuo Hsu, Jun-Lin Chiu, Chao-Kai Yu, *Jing-Jia Liou (National Tsing Hua Univ., Taiwan)
Pagepp. 797 - 802
Detailed information (abstract, keywords, etc)
Slides

9B-4 (Time: 17:05 - 17:30)
Title(Invited Paper) Application-Level Embedded Communication Tracer for Many-Core Systems
Author*Chih-Tsun Huang, Kuan-Chun Tasi, Jun-Shen Lin, Hsiao-Wei Chien (National Tsing Hua Univ., Taiwan)
Pagepp. 803 - 808
Detailed information (abstract, keywords, etc)


Session 9C  Building Secure Systems
Time: 15:50 - 17:30 Thursday, January 22, 2015
Location: Room 105
Chairs: Wenjing Rao (Univ. of Illinois, Chicago, U.S.A.), Sandip Ray (Intel, Portland, U.S.A.)

9C-1 (Time: 15:50 - 16:15)
TitleTiming-Based Anomaly Detection in Embedded Systems
AuthorSixing Lu, Minjun Seo, *Roman Lysecky (Univ. of Arizona, U.S.A.)
Pagepp. 809 - 814
Detailed information (abstract, keywords, etc)
Slides

9C-2 (Time: 16:15 - 16:40)
TitleSatisfiability Don't Care Condition Based Circuit Fingerprinting Techniques
Author*Carson J Dunbar, Gang Qu (Univ. of Maryland, U.S.A.)
Pagepp. 815 - 820
Detailed information (abstract, keywords, etc)
Slides

9C-3 (Time: 16:40 - 17:05)
TitleIC Piracy Prevention via Design Withholding and Entanglement
AuthorSoroush Khaleghi, Kai Da Zhao, *Wenjing Rao (Univ. of Illinois, Chicago, U.S.A.)
Pagepp. 821 - 826
Detailed information (abstract, keywords, etc)
Slides

9C-4 (Time: 17:05 - 17:30)
TitleVulnerability Analysis for Crypto Devices against Probing Attack
Author*Lingxiao Wei, Jie Zhang, Feng Yuan, Yannan Liu (Chinese Univ. of Hong Kong, Hong Kong), Junfeng Fan (Open Security Research, China), Qiang Xu (Chinese Univ. of Hong Kong, Hong Kong)
Pagepp. 827 - 832
Detailed information (abstract, keywords, etc)