| Title | NVPsim： A Simulator for Architecture Explorations of Nonvolatile Processors |
| Author | Yizi Gu, *Yongpan Liu, Yiqun Wang, Hehe Li, Huazhong Yang (Tsinghua University, China) |
| Page | pp. 147 - 152 |
| Keyword | nonvolatile processor, simulator, architecture exploration |
| Abstract | Nonvolatile processors (NVPs) preserve run-time information when power failure occurs by utilizing nonvolatile memory technologies. This feature enables
NVPs to make forward progress continuously under intermittent
power supply in energy harvesting systems. This paper builds a gem5 based NVP
simulator named NVPsim, which is validated against measured results of a
fabricated prototype with reasonable error rate. Furthermore, to demonstrate the capability of NVPsim for architecture exploration, we
evaluated performance and energy consumption of
different NVP designs varying in the choice of
nonvolatile memory for on-chip caches, the backup strategy and the energy
buffer size. Experimental results indicate that nvSRAM outperforms other
types of nonvolatile memory as the on-chip cache for energy harvesting systems. |
| Title | MCSSim: A Memory Channel Storage Simulator |
| Author | *Renhai Chen, Zili Shao (The Hong Kong Polytechnic University, Hong Kong), Chia-Lin Yang (National Taiwan University, Taiwan), Tao Li (University of Florida, U.S.A.) |
| Page | pp. 153 - 158 |
| Keyword | MCSSim, NVDIMMM, Memory Channel Storage |
| Abstract | Recently, NVDIMM (Non-Volatile Dual In-line Memory Module) is being widely supported by leading hardware design companies, such as IBM. Nevertheless, existing efforts largely focus on NVDIMM specification and fabrication issues, and the potential performance gains brought by NVDIMM are not fully investigated. In this paper, we present a NVDIMM based simulator called MCSSim to help study the memory channel storage techniques. MCSSim is a cycle-accurate simulator that is elaborated with the consideration of differences between the memory channel interface and the NAND flash memory features. MCSSim is also implemented with the DRAMSim2 [30] simulator thus enabling the simulation of a variety of hybrid memory systems by combining of DRAM DIMM and NVDIMM. We have done some experiments with MCSSim, and the experimental results show the effectiveness of the proposed simulator. |
| Title | Trace-Based Context-Sensitive Timing Simulation Considering Execution Path Variations |
| Author | *Sebastian Ottlik, Jan Micha Borrmann, Sadik Asbach, Alexander Viehl (FZI Research Center for Information Technology, Germany), Wolfgang Rosenstiel, Oliver Bringmann (University of Tübingen, Germany) |
| Page | pp. 159 - 165 |
| Keyword | Software Timing Simulation, Instruction Set Simulation, Software Performance Analysis |
| Abstract | We present a fast and accurate timing simulation of binary code execution on complex embedded processors.
Underlying block timings are extracted from a preceding hardware execution and differentiated by execution context.
Thereby, complex factors, such as caches, can be reflected accurately without explicit modelling.
Based on timings observed in one hardware execution, timing of numerous other executions for different inputs can be simulated at an average error below 5% for complex applications on an ARM Cortex-A9 processor. |
| Slides |
| Title | Generating High Coverage Tests for SystemC Designs Using Symbolic Execution |
| Author | *Bin Lin, Zhenkun Yang, Kai Cong, Fei Xie (Portland State University, U.S.A.) |
| Page | pp. 166 - 171 |
| Keyword | SystemC, Test Generation, Symbolic Execution, Coverage |
| Abstract | In this research, we have developed an approach to generating high coverage tests for SystemC designs using symbolic execution. We have applied this approach to a representative set of SystemC designs. The results show that our approach is able to generate tests that provide high code coverage of the designs with modest time and memory usage and to scale to designs of practical sizes. |
| Slides |