ASP-DAC 2019 accepted paper list ID Title 1004 Redeeming Chip-level Power Efficiency by Collaborative Management of the Computation and Communication 1009 A Heuristic for Multi Objective Software Application Mappings on Heterogeneous MPSoCs 1011 FACH: FPGA-based Acceleration of Hyperdimensional Computing by Reducing Computational Complexity 1014 Partitioned and Overhead-Aware Scheduling of Mixed-Criticality Real-Time Systems 1021 SIMULTime: Context-Sensitive Timing Simulation on Intermediate Code Representation for Rapid Platform Explorations 1022 Fully-automated Synthesis of Power Management Controllers from UPF 1024 Efficient Sparsification of dense circuit matrices in Model Order Reduction 1025 AERIS: Area/Energy-Efficient 1T2R ReRAM Based Processing-in-Memory Neural Network System-on-a-Chip 1026 Collaborative Accelerators for In-Memory MapReduce on Scale-up Machines 1029 Quantum Circuit Compilers Using Gate Commutation Rules 1031 A 0.16pJ/bit Recurrent Neural Network Based PUF for Enhanced Machine Learning Attack Resistance 1033 CompRRAE: RRAM-based Convolutional Neural Network Accelerator with Reduced Computations through a Runtime Activation Estimation 1035 SeRoHAL: Generation of Selectively Robust Hardware Abstraction Layers for Efficient Protection of Mixed-criticality Systems 1038 GRAM: Graph Processing in a ReRAM-based Computational Memory 1045 Bidirectional Tuning of Microring-Based Silicon Photonic Transceivers for Optimal Energy Efficiency 1051 BeSAT: Behavioral SAT-based Attack on Cyclic Logic Encryption 1054 Exclusive On-Chip Memory Architecture for Energy-Efficient Deep Learning Acceleration 1059 A Shape-Driven Spreading Algorithm Using Linear Programming for Global Placement 1064 HUBPA: High Utilization Bidirectional Pipeline Architecture for Neuromorphic Computing 1066 Log-Quantized Stochastic Computing for Memory and Computation Efficient DNNs 1069 Path Controllability Analysis for High Quality Designs 1070 Structural Rewriting in XOR-Majority Graphs 1079 Routing in Optical Network-on-Chip: Minimizing Contention with Guaranteed Thermal Reliability 1081 Sparsity for ReRAM: Pruning and Mapping Sparse Neural Network for ReRAM based Accelerator 1084 TAD: Time Side-Channel Attack Defense of Obfuscated Source Code 1089 Maximizing Power State Cross Coverage in Firmware-based Power Management 1093 ADEPOS: Anomaly Detection based Power Saving for Predictive Maintenance using Edge Computing 1098 ReRam-based Processing-in-Memory Architecture for Blockchain Platforms 1106 GraphSAR: A Sparsity-Aware Processing-in-Memory Architecture for Large-Scale Graph Processing on ReRAMs 1108 Implementing Neural Machine Translation with Bi-Directional GRU and Attention Mechanism on FPGAs Using HLS 1112 IR-ATA: IR Annotated Timing Analysis, A Flow for Closing the LoopBetween PDN design, IR Analysis & Timing Closure 1115 An N-Way Group Association Architecture and Sparse Data Group Association Load Balancing Algorithm for Sparse CNN Accelerators 1118 Efficient Sporadic Task Handling in Parallel AUTOSAR Applications Using Runnable Migration 1120 SeFAct: Selective Feature Activation and Early Classification for CNNs 1130 In-Memory Batch-Normalization for Resistive Memory based Binary Neural Network Hardware 1132 CycSAT-Unresolvable Cyclic Logic Encryption Using Unreachable States 1135 A High-Level Modeling and Simulation Approach Using Test-Driven Cellular Automata for Fast Performance Analysis of RTL NoC Designs 1140 TNPU: An Efficient Accelerator Architecture for Training Convolutional Neural Networks 1147 Aging-aware Chip Health Prediction: Adopting an Innovative Monitoring Strategy 1149 Efficient FPGA Implementation of Local Binary Convolutional Neural Network 1150 Leakage-Aware Thermal Management for Multi-Core Systems Using Piecewise Linear Model Based Predictive Control 1156 Improving Scan Chain Diagnostic Accuracy Using Multi-Stage Artificial Neural Networks 1160 Hardware-software Co-design of Slimmed Optical Neural Networks 1165 Execution of Provably Secure Assays on MEDA Biochips to Thwart Attacks 1166 A Sharing-Aware L1.5D Cache for Data Reuse in GPGPUs 1167 Detailed Routing by Sparse Grid Graph and Minimum-Area-Captured Path Search 1168 SRAF Insertion via Supervised Dictionary Learning 1170 Autonomous Vehicle Routing In Multiple Intersections 1172 On-chip Memory Optimization for High-level Synthesis of Multi-dimensional Data on FPGA 1180 NeuralHMC: An Efficient HMC-Based Accelerator for Deep Neural Networks 1181 Mosaic: An Automated Synthesis Flow for Boolean Logic Based on Memristor Crossbar 1185 Sample Preparation for Multiple-Reactant Bioassays on Micro-Electrode-Dot-Array Biochips 1186 ALook: Adaptive Lookup for GPGPU Acceleration 1187 CuckooPIM: An Efficient and Less-blocking Coherence Mechanism for Processing-in-Memory Systems 1191 Addressing the Issue of Processing Element Under-Utilization in General-Purpose Systolic Deep Learning Accelerators 1194 Testing Stuck-Open Faults of Priority Address Encoder in Content Addressable Memories 1195 Spectral Approach to Verifying Non-linear Arithmetic Circuits 1200 ScanSAT: Unlocking Obfuscated Scan Chains 1201 AxDNN:Towards the Cross-layer Design of Approximate DNNs 1209 BDD-based Synthesis of Optical Logic Circuits Exploiting Wavelenngth Division Multiplexing 1211 P3M: A PIM-based Neural Network Model Protection Scheme for Deep Learning Accelerator 1218 Towards Limiting the Impact of Timing Anomalies in Complex Real-Time Processors 1222 A Staircase Structure for Scalable and Efficient Synthesis of Memristor-Aided Logic 1223 Design Automation for Adiabatic Circuits 1224 Compiling SU(4) Quantum Circuits to IBM QX Architectures 1225 A Fast Machine Learning-based Mask Printability Predictor for OPC Acceleration 1232 Simulate-the-hardware: Training Accurate Binarized Neural Networks for Low-Precision Neural Accelerators 1233 Scalable Design for Field-coupled Nanocomputing Circuits 1236 Exploring emerging CNFET for Efficient Last Level Cache Design 1242 Phone-nomenon: A System-Level Thermal Simulator for Handheld Devices 1243 ROBIN: Incremental Oblique Interleaved ECC for Reliability Improvement in STT-MRAM Caches 1244 Multi-Angle Bended Heat Pipe Design using X-Architecture Routing with Dynamic Thermal Weight on Mobile Devices 1246 Virtual Prototyping of Heterogeneous Automotive Applications: Matlab, SystemC, or both? 1248 Thermal-aware 3D Symmetrical Buffered Clock Tree Synthesis 1252 S2PM: Semi-Supervised Learning for Ef?cient Performance Modeling of Analog and Mixed Signal Circuits 1253 Robust Sample Preparation on Low-Cost Digital Microfluidic Biochips 1258 Cell Division: Weight Bit-Width Reduction Technique for Convolutional Neural Network Hardware Accelerators 1265 Hybrid Binary-Unary Hardware Accelerator 1267 A Figure of Merit for Assertions in Verification 1268 Suspect2vec: A Suspect Prediction Model for Directed RTL Debugging 1269 Diffusion Break-Aware Leakage Power Optimization and Detailed Placement in sub-10nm VLSI 1278 Latency Constraint Guided Buffer Sizing and Layer Assignment for Clock Trees with Useful Skew 1281 Handling Stuck-at-faults in Memristor Crossbar Arrays using Matrix Transformations 1285 Layout Recognition Attacks on Split Manufacturing 1287 Finding Placement-Relevant Clusters With Fast Modularity-Based Clustering 1289 Energy-Efficient, Low-Latency Realization of Neural Networks through Boolean Logic Minimization 1291 Learning-Based Prediction of Package Power Delivery Network Quality 1294 Semi-Supervised Hotspot Detection with Self-Paced Multi-Task Learning 1295 SAADI: A Scalable Accuracy Approximate Divider for Dynamic Energy-Quality Scaling 1297 CAPTOR: A Class Adaptive Filter Pruning Framework for Convolutional Neural Networks in Mobile Applications 1299 REIN: A Robust Training Method for Enhancing Generalization Ability of Neural Networks in Autonomous Driving Systems 1302 ParaPIM: A Parallel Processing-in-Memory Accelerator for Binary-Weight Deep Neural Networks 1305 MDP-trees: Multi-Domain Macro Placement for Ultra Large-Scale Mixed-Size Designs 1311 Modeling Processor Idle Times in MPSoC Platforms to Enable Integrated DPM, DVFS, and Task Scheduling Subject to a Hard Deadline 1319 An Approximation Algorithm to the Optimal Switch Control of Reconfigurable Battery Packs 1323 Boosting Chipkill Capability under Retention-Error Induced Reliability Emergency 1329 Towards Practical Homomorphic Email Filtering: A Hardware-Accelerated Secure Naive Bayesian Filter 1332 Tackling Signal Electromigration with Learning-Based Detection and Multistage Mitigation 1334 Factorization Based Dilution of Biochemical Fluids with Micro-Electrode-Dot-Array Biochips