ASP-DAC 2021 Accepted Paper List ID Title 1009 Attacking a CNN-based Layout Hotspot Detector Using Group Gradient Method 1010 ATM: A High Accuracy Extracted Timing Model for Hierarchical Timing Analysis 1011 Arbitrary and Variable Precision Floating Point Arithmetic Support in Dynamic Binary Translation 1015 Simulation of Ideally Switched Circuits in SystemC 1018 Net2: A Graph Attention Network Method Customized for Pre-Placement Net Length Estimation 1019 A reduced-precision streaming SpMV architecture for Personalized PageRank on FPGA 1021 A Non-Volatile Computing-In-Memory Framework With Margin Enhancement Based CSA and Offset Reduction Based ADC 1023 Normalized Stability: A Cross-Level Design Metric for Early Termination in Stochastic Computing 1027 Area Efficient Functional Locking through Coarse Grained Runtime Reconfigurable Architectures 1036 A Dynamic Link-latency Aware Cache Replacement Policy (DLRP) 1043 A Low Cost Weight Obfuscation Scheme for Security Enhancement of ReRAM Based Neural Network Accelerators 1046 Optimizing Inter-Core Data-Propagation Delays in Industrial Embedded Systems under Partitioned Scheduling 1047 A Novel Technology Mapper for Complex Universal Gates 1050 SAC: A Stream Aware Write Cache Scheme forMulti-Streamed Solid State Drives 1051 GRA-LPO: Graph Convolution Based Leakage PowerOptimization 1053 Boosting Pin Accessiblity Through Cell Layout Topology Diversification 1058 A Decomposition-Based Synthesis Algorithm for Sparse Matrix-Vector Multiplication in Parallel Communication Structure 1061 Energy-Performance Co-Management of Mixed-Sensitivity Workloads on Heterogeneous Multi-core Systems 1065 Exploiting Extended Krylov Subspace for the Reduction of Regular and Singular Circuit Models 1070 Manufacturing-Aware Power Staple Insertion Optimization by Enhanced Multi-Row Detailed Placement Refinement 1073 Bridging the Frequency Gap in Heterogeneous 3D SoCs through Technology-Specific NoC Router Architectures 1075 A General Equivalence Checking Framework for Multivalued Logic 1077 An Efficient Approximate Node Merging with an Error Rate Guarantee 1080 Machine Learning-based Structural Pre-route Insertability Prediction and Improvement with Guided Backpropagation 1083 Exploiting Quantum Teleportation in Quantum Circuit Mapping 1085 Efficient Accuracy Recovery in Approximate Neural Networks by Systematic Error Modelling 1088 Random Stimuli Generation for the Verification of Quantum Circuits 1089 Bayesian Inference on Introduced General Region: An Efficient Parametric Yield Estimation Method for Integrated Circuits 1092 ATLaS: Automatic Detection of Timing-based Information Leakage Flows for SystemC HLS Designs 1093 A Novel DRAM-Based Process-in-Memory Architecture and its Implementation for CNNs 1095 Connection-based Processing-In-Memory Engine Design Based on Resistive Crossbars 1099 Facilitating the Efficiency of Secure File Data and Metadata Deletion on SMR-based Ext4 File System 1108 Constrained Conservative State Symbolic Co-analysis for Ultra-low-power Embedded Systems 1113 RIME: A Scalable and Energy-Efficient Processing-In-Memory Architecture for Floating-Point Operation 1115 Mode-wise Voltage-scalable Design with Activation-aware Slack Assignment for Energy Minimization 1118 Gravity: An Artificial Neural Network Compiler for Embedded Applications 1135 Breaking Analog Biasing Locking Techniques via Re-Synthesis 1136 Hardware-Aware NAS Framework with Layer Adaptive Scheduling on Embedded System 1138 A Heretical Assessment Strategy on Soft Error Propagation in Deep Learning Controller 1141 Efficient Techniques for Training the Memristor-based Spiking Neural Networks Targeting Better Speed, Energy and Lifetime 1142 A Quantized Training Framework for Robust and Accurate ReRAM-based Neural Network Accelerators 1144 Algebraic and Boolean Optimization Methods for AQFP Superconducting Circuits 1152 Accurate and Efficient Simulation of Microfluidic Networks 1154 Light: A Scalable and Efficient Wavelength-Routed Optical Networks-On-Chip Topology 1155 An Adaptive Delay Model for Timing Yield Estimation under Wide-Voltage Range 1157 Combining Memory Partitioning and Subtask Generation for Parallel Data Access on CGRAs 1160 One-Pass Synthesis for Field-coupled Nanocomputing Technologies 1161 Design Space Exploration of Heterogeneous-Accelerator SoCs with Hyperparameter Optimization 1162 A Multiple-Precision Multiply and Accumulation Design with Multiply-Add Merged Strategy for AI Accelerating 1170 1st-Order to 2nd-Order Threshold Logic Gate Transformation with an Enhanced ILP-based Identification Method 1173 A Write-friendly Arithmetic Coding Scheme for Achieving Energy-Efficient Non-Volatile Memory Systems 1174 Block-Circulant Neural Network Accelerator Featuring Fine-Grained Frequency-Domain Quantization and Reconfigurable FFT Modules 1176 Layout Symmetry Annotation for Analog Circuits with Graph Neural Networks 1178 Dataflow-Architecture Co-Design for 2.5D DNN Accelerators using Wireless Network-on-Package 1179 On the Impact of Aging on Power Analysis Attacks Targeting Power-Equalized Cryptographic Circuits 1183 A Fast Yet Accurate Message-level Communication Bus Model for Timing Prediction of SDFGs on MPSoC 1186 Aging Aware Request Scheduling for Non-Volatile Main Memory 1188 MIPAC: Dynamic Input-Aware Accuracy Control for Dynamic Auto-Tuning of Iterative Approximate Computing 1192 Zero Correlation Error: A Metric for Finite-Length Bitstream Independence in Stochastic Computing 1193 Automated Test Generation for Hardware Trojan Detection using Reinforcement Learning 1194 DEF: Differential Encoding of Featuremaps for Low Power Convolutional Neural Network Accelerators 1199 Standard Cell Routing with Reinforcement Learning and Genetic Algorithm in Advanced Technology Nodes 1200 LiteIndex: Memory-Efficient Schema-Agnostic Indexing for JSON documents in SQLite 1205 Power-Efficient Layer Mapping for CNNs on Integrated CPU and GPU Platforms: A Case Study 1206 Accelerate Non-unit Stride Convolutions with Winograd Algorithms 1207 Dynamic Programming Assisted Quantization Approaches for Compressing Normal and Robust DNN Models 1212 Analog IC Aging-induced Degradation Estimation via Heterogeneous Graph Convolutional Networks 1214 Prediction of Register Instance Usage and Time-sharing Register for Extended Register Reuse Scheme 1215 Puncturing the memory wall: Joint optimization of network compression with approximate memory for ASR application 1218 DeepOpt: Optimized Scheduling of CNN Workloads for ASIC-based Systolic Deep Learning Accelerators 1219 DP-Sim: A Full-stack Simulation Infrastructure for Digital Processing In-Memory Architectures 1221 Energy-Aware Design Methodology for Myocardial Infarction Detection on Low-Power Wearable Devices 1229 HW-BCP: A Custom Hardware Accelerator for SAT Suitable for Single Chip Implementation for Large Benchmarks 1230 A Timing Prediction Framework for Wide Voltage Design with Data Augmentation Strategy 1240 Value-Aware Error Detection and Correction for SRAM Buffers in Low-Bitwidth, Floating-Point CNN Accelerators 1241 Placement for Wafer-Scale Deep Learning Accelerator 1247 Multi-FPGA Co-optimization: Hybrid Routing and Competitive-based Time Division Multiplexing Assignment 1249 HyperRec: Efficient Recommender Systems with Hyperdimensional Computing 1250 Learning Boolean Circuits from Examples for Approximate Logic Synthesis 1252 Optimizing Temporal Decoupling using Event Relevance 1261 TreeNet: Deep Point Cloud Embedding for Routing Tree Construction 1265 Cache-Aware Dynamic Skewed Tree for Fast Memory Authentication 1266 FePIM: Contention-Free In-Memory Computing Based on Ferroelectric Field-Effect Transistors 1270 EHDSktch: A Generic Low Power Architecture for Sketching in Energy Harvesting Devices 1273 A Unified Printed Circuit Board Routing Algorithm With Complicated Constraints and Differential Pairs 1275 BatchSizer: Power-Performance Trade-off for DNN Inference 1276 VADER: Leveraging the Natural Variation of Hardware to Enhance Adversarial Attack 1284 Dynamical Decomposition and Mapping of MPMCT gates to Nearest Neighbor Architectures 1288 Attention-in-Memory for Few-Shot Learning with Configurable Ferroelectric FET Arrays 1289 Interference-free Design Methodology for Paper-Based Digital Microfluidic Biochips 1292 Providing Plug N' Play for Processing-in-Memory Accelerators 1296 A multi-commodity network flow based routing algorithm for paper-based digital microfluidic biochips 1301 ObfusX: Routing Obfuscation with Explanatory Analysis of a Machine Learning Attack 1309 DNR: A Single-Shot Tunable Robust Pruning Framework Through Dynamic Network Rewiring of DNNs 1315 High-Level Synthesis of Transactional Memory 1318 Entropy-Based Modeling for Estimating Adversarial Bit-flip Attack Impact on Binarized Neural Network 1319 Temperature-Aware Optimization of Monolithic 3D Deep Neural Network Accelerators 1323 Thermal and IR Drop Analysis Using Convolutional Encoder-Decoder Networks 1324 System-Level Verification of Linear and Non-Linear Behaviors of RF Amplifiers using Metamorphic Relations 1327 Residue-Net: Multiplication-free Neural Network by In-situ, No-loss Migration to Residue Number Systems 1331 Mutation-based Compliance Testing for RISC-V 1335 Exploiting HLS-Generated Multi-Version Kernels to Improve CPU-FPGA Cloud Systems 1337 Read your Circuit: Leveraging Word Embedding to Guide Logic Optimization 1340 PCBench: Benchmarking of Board-Level Hardware Attacks and Trojans 1350 Canonical Huffman Decoder on Fine-grain Many-core Processor Arrays 1354 Energy and QoS-Aware Dynamic Reliability Management of IoT Edge Computing Systems 1361 A Self-Test Framework for Detecting Fault-induced Accuracy Drop in Neural Network Accelerators 1367 Mixed Precision Quantization for ReRAM-based DNN Inference Accelerators 1232 A Robust Batch Bayesian Optimization for Analog Circuit Synthesis via Local Penalization 1325 Fast and Efficient Constraint Evaluation of Analog Layout using Machine Learning Models 1359 Automatic Surrogate Model Generation and Debugging of Analog/Mixed-Signal Designs Via Collaborative Stimulus Generation and Machine Learning