This year for the first time ASPDAC will host a poster session for Ph

ASP-DAC 2005 Ph.D. Forum Information

This year for the first time ASPDAC will host a poster session for Ph.D. students to present their research work. This is a great opportunity for students to get feedback and have discussion with people from academia and industry. Accepted students can attend ASP-DAC free. Travel grants may be available for some of the students attending the forum.

Eligibility

Students must have at least one published paper and must be within 1-2 years of completing their dissertations. Students who have presented previously at DAC’s or DATE's Ph.D. Forums are not eligible.

Important Dates

Submission Deadline: July 22 (Thu), 2004
Notification Date: September 30 (Thu), 2004
Forum Presentation: To Be Announced

Submission

Requirements:

Abstract of the dissertation including name of the student and advisor, institution, contact information, estimated graduation date, track number, figures, tables and bibliography (if applicable). The abstract must be at most two pages (this is a hard limit).
A list of all papers related to the dissertation authored by the student.
A published supporting paper authored by the student and related to the dissertation.
Please send the above to Dr. Farzan Fallah: farzan @ fla. fujitsu.com.

Format:

The abstract must be in .pdf or .ps formats (.pdf format is preferable). The font should not be smaller than 10 points. Please make sure all pages print well.
The abstract must be well organized and should not have any spelling error.
The bibliography and the list of published papers must be in IEEE style (See http://www.computer.org/author/style/refer.htm).

Tracks:

The tracks are identical to ASPDAC’s tracks.

1. System Level Design Methodology

System VLSI and SOC design methods, System specification, Specification languages, Design languages, Design reuse and IPs , Core-based design, Rapid prototyping, Low power system design, etc.

2. Embedded and Real-Time Systems

Hardware-software co-design, Co-simulation, Co-verification, Real-time OS and middleware, Design language for embedded systems, Compilation Techniques, etc.

3. Behavioral / Logic Synthesis and Optimization

Behavioral / RT synthesis, Optimization techniques in logic design, Library mapping, Interaction between logic design and layout, IP-core design, Sequential and asynchronous logic synthesis, Hardware algorithms, etc.

4. Validation and Verification for Behavioral / Logic Design

Logic simulation, Simulation engine, Symbolic simulation, Formal verification, Binary decision diagram, Equivalence checking, Transaction-level / RTL and gate level modeling and validation, etc.

5. Circuit Optimization and Simulation

Circuit modeling, Circuit simulation, Circuit extraction, Cell library characterization and generation, Circuit characterization, Clock / power / ground distribution, Signal integrity issues, etc.

6. Physical Design and Interconnect Optimization

Physical synthesis, Floor-planning, Wire optimization and planning, Partitioning, Placement, Global / Detail routing, Module generation, New layout algorithms, Interconnect issues, etc.

7. Test and Design for Testability

Test design, Test pattern generation, BIBS, Fault simulation, Fault modeling, Test method for core-based design, Test issues on IP cores, Memory testing, VLSI tester, etc.

8. Analog and RF Circuit Design

Analog circuit synthesis, Analog layout, Verification, Simulation techniques, Noise analysis, Analog circuit testing, Analog digital mixed design, etc.

9. Design for Manufacturability and TCAD

Device modeling, Device simulation, Parameter extraction, Process modeling, Process simulation, Yield optimization, Device testing, etc.

10. Reconfigurable Systems

Field-programmable gate array (FPGA) design, FPGA design tools, Novel reconfigurable systems, Synthesis and mapping techniques for reconfigurable systems, Application of reconfigurable systems, etc.

11. Leading Edge Designs