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ASP-DAC 2006 Archives
1C-1
| Title | Robust Analytical Gate Delay Modeling for Low Voltage Circuits |
| Author | Anand Ramalingam (The University of Texas at Austin, United States), Sreekumar V. Kodakara (The University of Minnesota, United States), Anirudh Devgan (Magma Design Automation, United States), *David Z. Pan (The University of Texas at Austin, United States) |
| Abstract | Sakurai-Newton (SN) delay metric [1] is the most widely used closed form delay metric for CMOS gates due to its simplicity and reasonable accuracy. However, it can be shown that the SN metric fails to provide high accuracy and fidelity when CMOS gates operate at low supply voltages. Thus it may not be applicable in many low power applications with voltage scaling. In this paper, we propose a new closed form delay metric based on the centroid of power dissipation. This new metric is inspired by our key observation and theoretic proof that the SN delay is indeed Elmore delay, which can be viewed as the centroid of current. Our proposed metric has a very high correlation coefficient (0.98) when correlated with the actual delays got from the HSPICE simulations. Such high correlation is consistent across all major process technologies (180; 130; 100; 65; and 45nm). In comparison, the SN metric has a correlation coefficient between (0.70; 0.90) depending upon the technology and the CMOS gate, and it is less accurate for lower supply voltages. Since our proposed metric has high fidelity across a wide range of supply voltages yet a simple closed form, it will be very useful to guide low voltage and low power designs |
| Slides (pdf file) | 1C-1 |
1C-2
| Title | CGTA: Current Gain-based Timing Analysis for Logic Cells |
| Author | Shahin Nazarian, *Massoud Pedram (University of Southern California, United States), Tao Lin, Emre Tuncer (Magma, United States) |
| Abstract | This paper introduces a new current-based cell timing analyzer, called CGTA, which has a higher performance than existing logic cell timing analysis tools. CGTA relies on a compact lookup table storing the output current gain (sensitivity) of every logic cell as a function of its input voltage and output load. The current gain values are subsequently used by the timing calculator to produce the output current value as a function of the applied input voltage. This current and the output load then uniquely determine the output voltage value. Therefore, CGTA is capable of efficiently and accurately computing the output voltage waveform of a logic cell, which has been subjected to an arbitrary noisy input voltage waveform. Experimental results are presented to assess the quality of CGTA compared to other existing approaches. |
| Slides (pdf file) | 1C-2 |
1C-3
| Title | Efficient Static Timing Analysis Using a Unified Framework for False Paths and Multi-Cycle Paths |
| Author | Shuo Zhou, Bo Yao, Hongyu Chen, Yi Zhu, *Chung-Kuan Cheng (University of California, San Diego, United States), Mike Hutton (Altera Corp., United States) |
| Abstract | We propose a framework to unify the process of false paths and multi-cycle paths in static timing analysis (STA). We use subgraphs attached with timing constraints to represent false paths and multi-cycle paths. The complexity of the subgraph representation is reduced to improve efficiency. Finally, we present theorems to show that the unified framework produces correct timings. The experimental results demonstrate that the minimization is effective for both artificial and industry test cases. |
| Slides (pdf file) | 1C-3 |
1C-4
| Title | Crosstalk Analysis using Reconvergence Correlation |
| Author | *Sachin Shrivastava, Rajendra Pratap, Harindranath Parameswaran, Manuj Verma (Cadence Design Systems, India) |
| Abstract | This paper targets at the reduction of false violations during crosstalk analysis by using topological correlation in the design. Pessimism reduction helps in reducing the overall design cycle time by avoiding many noise-fix iterations. We introduce the concept of relative timing windows and suggest a method for doing crosstalk analysis using relative timing windows. We have analyzed the effectiveness of the approach statistically. Some results on real designs are also presented which shows reduction in number of violation using the new approach. |
| Slides (pdf file) | 1C-4 |
1C-5
| Title | Process-Induced Skew Reduction in Nominal Zero-Skew Clock Trees |
| Author | *Matthew R. Guthaus, Dennis Sylvester (University of Michigan, United States), Richard B. Brown (University of Utah, United States) |
| Abstract | This work develops an analytic framework for clock tree analysis considering process variations that is shown to correspond well with Monte Carlo results. The analysis framework is used in a new algorithm that constructs deterministic nominal zero-skew clock trees that have reduced sensitivity to process variation. The new algorithm uses a sampling approach to perform route embedding during a bottom-up merging phase, but does not select the best embedding until the top-down phase. This results in clock trees that exhibit a mean skew reduction of 32.4% on average and a standard deviation reduction of 40.7% as verified by Monte Carlo. The average increase in total clock tree capacitance is less than 0.02%. |
| Slides (pdf file) | 1C-5 |