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ASP-DAC 2006 Archives
1D-1
| Title | A Low Dynamic Power and Low Leakage Power 90-nm CMOS Square-Root Circuit |
| Author | *Tadayoshi Enomoto, Nobuaki Kobayashi (Chuo University, Japan) |
| Abstract | To drastically reduce the dynamic power (PAT) and the leakage power (PST), while to keep speed of a CMOS square-root (SR) circuit, a new algorithm, new architectures and a new leakage reduction circuit were developed. Using these techniques, a 90-nm CMOS LSI was fabricated. The PAT and PST of the new SR circuit were reduced to about 1/4 and 1/33 those of a conventional SR circuit. Measured results agreed well with simulated results. |
| Slides (pdf file) | 1D-1 |
1D-2
| Title | A High-Throughput Low-Power Fully Parallel 1024-bit 1/2-Rate Low Density Parity Check Code Decoder in 3-Dimensional Integrated Circuits |
| Author | Lili Zhou, Cherry Wakayama, Nuttorn Jangkrajarng, Bo Hu, *Richard Shi (University of Washington, United States) |
| Abstract | A 1024-bit, ½-rate fully parallel low-density parity-check (LDPC) code decoder has been designed and implemented using a three-dimensional (3D) 0.18mm fully depleted silicon-on-insulator (FDSOI) CMOS technology based on wafer bonding. The taped-out 3D decoder with about 8M transistors was simulated to have a high throughput of 2Gb/s and a low power consumption of only 430mW using 6.4mm by 6.3mm of die area. The 3D implementation is estimated to offer more than 10x power-delay-area product improvement over its corresponding 2D implementation. This first large-scale 3D ASIC with fine-grain (5mm) vertical interconnects is made possible by jointly developing a complete automated 3D design flow from a commercial 2-D design flow combined with the needed 3D-design point tools. |
| Slides (pdf file) | 1D-2 |
1D-3
| Title | A 16-Bit, Low-Power Microsystem with Monolithic MEMS-LC Clocking |
| Author | *Robert M. Senger, Eric D. Marsman, Michael S. McCorquodale (University of Michigan, United States), Richard B. Brown (University of Utah, United States) |
| Abstract | Single-chip systems save the power dissipation that would be required for chip-to-chip communication, resulting in compact, low-power solutions for battery-powered applications. This paper describes the design and measured performance of a fully-functional digital core with a low-jitter, on-chip, MEMS-LC clock reference. This chip has been fabricated in TSMC’s 0.18um MM/RF bulk CMOS process. Maximum power consumption of the complete microsystem is 48.78mW operating at 90MHz on a 1.8V power supply. |
| Slides (pdf file) | 1D-3 |
1D-4
| Title | Ultra-Low Voltage Power Management Circuit and Computation Methodology for Energy Harvesting Applications |
| Author | Chi-Ying Tsui, *Hui Shao, Wing-Hung Ki, Feng Su (Hong Kong University of Science and Technology, Hong Kong) |
| Abstract | A power management and computation methodology is proposed for ultra-low power energy harvesting applications. An integrated exponential charge pump that accepts an input voltage of around 150mV and provides an unregulated output voltage of more than 1.5V serves as the power supply. To cater with the fluctuated energy source and unregulated power supply, a supply side charge-based computation methodology is proposed, of which the computation activity tracks with the fluctuation of the available energy. The idea is demonstrated in a test chip fabricated using a 0.35um technology. |
| Slides (pdf file) | 1D-4 |
1D-5
| Title | A 0.5-V Sigma-Delta Modulator Using Analog T-Switch Scheme for the Subthreshold Leakage Suppression |
| Author | *Koichi Ishida, Atit Tamtrakarn, Takayasu Sakurai (University of Tokyo, Japan) |
| Abstract | A 0.5-V sigma-delta modulator implemented in a 0.15-€Î FD-SOI process with low VTH of 0.1V using analog T-switch (AT-switch) scheme to suppress subthreshold-leakage problems is presented. The scheme is compared with the conventional circuit, which are also fabricated in the same chip. The measurement result demonstrates that the sigma-delta modulator based on AT-switch realizes 6-bit resolution through reducing non-linear leakage effects while the conventional circuit can achieve 4-bit resolution. |
| Slides (pdf file) | 1D-5 |
1D-6
| Title | An Implementation of a CMOS Down-Conversion Mixer for GSM1900 Receiver |
| Author | *Fangqing Chu, Wei Li, Junyan Ren (Fudan University, China) |
| Abstract | A 1.9-GHz down-conversion CMOS mixer, intended for the GSM1900 (PCS1900) Low-IF receivers is present with the utilization of novel folded Gilbert Cell fabricated in a RF 0.18-µm CMOS process. The prototype demonstrates a good performance. It achieves a conversion gain of 6dB, SSB Noise Figure of 18.5dB and IIP3 11.5dBm while consuming 7mA current from 3.3V power supply. |
| Slides (pdf file) | 1D-6 |
1D-7
| Title | Integrated Direct Output Current Control Switching Converter using Symmetrically-Matched Self-Biased Current Sensors |
| Author | *Yat-Hei Lam (Hong Kong University of Science and Technology, Hong Kong), Suet-Chui Koon (National Semiconductor Corporation, Hong Kong), Wing-Hung Ki, Chi-Ying Tsui (Hong Kong University of Science and Technology, Hong Kong) |
| Abstract | A non-inverting flyback converter using an integrated symmetrically-matched self-biased current sensor was fabricated in a 0.35m CMOS process. It operates in pseudo-continuous conduction mode and employs a direct output current control scheme to achieve excellent line transient response. The converter switches at 1MHz with an input of 1.2V to 2V to give an output of 1.5V and delivers 250mA. |
| Slides (pdf file) | 1D-7 |
1D-8
| Title | Adaptively-Biased Capacitor-Less CMOS Low Dropout Regulator with Direct Current Feedback |
| Author | *Yat-Hei Lam, Wing-Hung Ki, Chi-Ying Tsui (Hong Kong University of Science and Technology, Hong Kong) |
| Abstract | A capacitor-less low dropout regulator (LDR) with direct current feedback is proposed. A symmetrically-matched voltage mirror in sensing the load current is employed, and gives an excellent line and load regulation. The dynamic biasing results in an LDR with pole-tracking that extends the bandwidth of the loop gain at high load currents. The LDR with active circuit area of 0.11mm2 was fabricated in a 0.35μm CMOS process. Measurement results demonstrated the good performance of the LDR.. |
| Slides (pdf file) | 1D-8 |
1D-9
| Title | A Built-in Power Supply Noise Probe for Digital LSIs |
| Author | *Mitsuya Fukazawa, Koichiro Noguchi, Makoto Nagata, Kazuo Taki (Kobe University, Japan) |
| Abstract | A design of compact noise detector circuitry that can be embedded and arrayed within a highdensity large-scale digtal circuit is demonstrated, with a prototype chip using 0.18 um CMOS technology. |
| Slides (pdf file) | 1D-9 |
1D-10
| Title | A 476-gate-count Dynamic Optically Reconfigurable Gate Array VLSI chip in a standard 0.35um CMOS Technology |
| Author | *Minoru Watanabe, Fuminori Kobayashi (Kyushu Institute of Technology, Japan) |
| Abstract | Optically Reconfigurable Gate Arrays (ORGAs) can easily enable both fast reconfiguration and numerous reconfiguration contexts by using an optical holographic memory and optical wide-band reconfiguration connections. Such devices present the possibility of large virtual gate-count VLSIs. This paper presents a new design of a 476-gate-count Dynamic Optically Reconfigurable Gate Array (DORGA) modified from a previously designed 68-gate-count DORGA using standard 0.35 um three-metal CMOS process technology. |
| Slides (pdf file) | 1D-10 |
1D-11
| Title | Measurement Results of Within-Die Variations on a 90nm LUT Array for Speed and Yield Enhancement of Reconfigurable Devices |
| Author | *Kazuya Katsuki, Manabu Kotani, Kazutoshi Kobayashi, Hidetoshi Onodera (Graduate School of Informatics, Kyoto University, Japan) |
| Abstract | It is possible to enhance speed and yield of reconfigurable devices utilizing WID variations. An LUT array LSI is fabricated on a 90nm process to measure WID and D2D variations. Performance fluctuations are measured by counting the number of LUTs through which a signal is passing within a certain time. D2D and WID variations are clearly observed by the measurement. |
| Slides (pdf file) | 1D-11 |
1D-12
| Title | High-Throughput Decoder for Low-Density Parity-Check Code |
| Author | *Tatsuyuki Ishikawa, Kazunori Shimizu, Takeshi Ikenaga, Satoshi Goto (Graduate School of Information, Production and Systems, Waseda University, Japan) |
| Abstract | We have designed and implemented the LDPC decoder chip with memory-reduction method to achieve high-throughput and practical chip size. The decoder decodes (3,6)-2304bit regular LDPC codes using modified min-sum algorithm. The decoder achieves a throughput of 530Mb/s at an operating frequency of 147MHz. The chip is fabricated in a 0.18um, 6 metal-layer CMOS technology. The chip size is 36mm^2. |
| Slides (pdf file) | 1D-12 |
1D-13
| Title | Hardware Implementation of Super Minimum All Digital FM Demodulator |
| Author | *Nursani Rahmatullah, Arif Nugroho (Institut Teknologi Bandung, Indonesia) |
| Abstract | We propose improvement of the new architecture of digital FM demodulator. This work enhances signal quality, system clock frequency, and superior than well known PLL technique today. No more multiplier, no more ROM or table, compact size, and very fast in transient or state response. Real implementation in Altera® APEX20K200 EBC652-1X PLD gives 348 logic elements and run up to 224.42 MHz. |
| Slides (pdf file) | 1D-13 |
1D-14
| Title | Designing a Custom Architecture for DCT Using NISC Technology |
| Author | Bita Gorjiara, Mehrdad Reshadi, *Daniel Gajski (University of California, Irvine, United States) |
| Abstract | This paper presents design of a custom architecture for Discrete Cosine Transform (DCT) using No-Instruction-Set Computer (NISC) technology that is developed for fast processor customization. Using several software transformations and hardware customization, we achieved up to 10 times performance improvement, 2 times power reduction, 12.8 times energy reduction, and 3 times area reduction compared to an already-optimized soft-core MIPS implementation. |
| Slides (pdf file) | 1D-14 |
1D-15
| Title | A 52mW 1200MIPS Compact DSP for Multi-Core Media SoC |
| Author | *Shih-Hao Ou, Tay-Jyi Lin, Chao-Wei Huang, Yu-Ting Kuo, Chie-Min Chao, Chih-Wei Liu (National Chiao Tung University, Taiwan), Chein-Wei Jen (STC, ITRI, Taiwan) |
| Abstract | This paper presents a fully-programmable DSP for multi-core media SoC, which has been optimized to execute a set of signal processing kernels very efficiently. It has a novel data-centric instruction set and the corresponding latency-insensitive micro-architecture, and is optimized concurrently with its automatic software generator. The DSP can achieve 3X performance (in cycles) of those found in commercial dual-core application processors with similar computing resources. It has been implemented in the UMC 0.18¡ÂÎ 1P6M CMOS technology and can operate at 314MHz while consuming only 52mW average power. |
| Slides (pdf file) | 1D-15 |
1D-16
| Title | Implementation of H.264/AVC Decoder for Mobile Video Applications |
| Author | *Suh Ho Lee, Ji Hwan Park, Seon Wook Kim, Sung Jea Ko, Suki Kim (Korea University, Republic of Korea) |
| Abstract | This paper presents an H.264 baseline profile decoder based on an SOC platform design methodology. The overall decoding throughput is increased by optimized software and a dedicated hardware accelerator. We minimize the number of bus accesses and use macroblock (MB) level pipeline processing techniques to achieve a real time operation. We implemented and verified a prototype on an SOC platform with a 32-bit RISC CPU core and FPGA module. Our design can process up to 20 frames/sec with QCIF_(176x144). The proposed architecture can be easily applied to many mobile video application areas such as a digital camera and a DMB (Digital Multimedia Broadcasting) phone. |
| Slides (pdf file) | No slides |
1D-17
| Title | A High-Performance Platform-Based SoC for Information Security |
| Author | Min Wu, Xiaoyang Zeng, *Jun Han, Yongyi Wu, Yibo Fan (State Key Lab of ASIC and System, Fudan University, China) |
| Abstract | A platform-based SoC named as Firebird is presented in this paper, which is used for the applications of information security. Several design aspects, which includes the embedded 32-bit RISC CPU and AMBA bus system, the reconfigurable and scalable public-key crypto-coprocessor, high-performance TRNG and several low-power schemes, make Firebird very efficient for the client-end applications of information security. Also the test results of this prototype chip indicate that Firebird can work with all these features efficiently, and has some obvious advantages over other designs in the literatures. |
| Slides (pdf file) | 1D-17 |
1D-18
| Title | Configurable Multi-Processor Architecture and its Processor Element Design |
| Author | *Tsutomu Nishimura, Takuji Miki, Hiroaki Sugiura, Yuki Matsumoto, Masatsugu Kobayashi (Ritsumeikan University, Japan), Toshiyuki Kato, Tsutomu Eda (VLSI center, Ritsumeikan University, Japan), Hironori Yamauchi (Ritsumeikan University, Japan) |
| Abstract | We developed an application specific multi-processor generation system intended for real-time applications. In this system, we adopted a distributed memory type multi-processor architecture with hierarchical tree network as a configurable multi-processor which can be adapted to various scale systems flexibly. We have also developed a configurable multi-processor prototype as LSI chips with the 0.18 micro meter CMOS standard cell technology. |
| Slides (pdf file) | 1D-18 |
1D-19
| Title | Design and Implementation of Transducer for ARM-TMS Communication |
| Author | Hansu Cho, Samar Abdi, *Daniel Gajski (University of California, Irvine, United States) |
| Abstract | Communication between components, with different interface protocols, requires an extra component that must translate one protocol to another. This component is referred to as a transducer. In this paper we describe the design and implementation of a transducer between AMBA bus and TMS DSP bus. The transducer allows system designers to send data from AMBA compliant components to TMS compliant ones, and vice versa. The transducer was modeled in Verilog and implemented on Xilinx VirtexII FPGA board. |
| Slides (pdf file) | 1D-19 |