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ASP-DAC 2006 Archives
4C-1
| Title | A Quasi-Newton Preconditioned Newton-Krylov Method for Robust and Efficient Time-Domain Simulation of Integrated Circuits with Strong Parasitic Couplings |
| Author | Zhao Li (Cadence Design Systems, United States), *Richard Shi (University of Washington, United States) |
| Abstract | In this paper, the Newton-Krylov method is explored for robust and efficient time-domain VLSI circuit simulation. Different from the LU-factorization based direct method, the Newton-Krylov method uses a preconditioned Krylov-subspace iterative method for linear system solving. Our key contribution is to introduce an effective quasi-Newton preconditioning scheme for Krylov-subspace methods to reduce the number and cost of LU factorizations during time-domain circuit simulation. Experimental results on a collection of digital, analog and RF circuits have shown that the quasi-Newton preconditioned Krylov-subspace method is as robust and accurate as SPICE3. The proposed Newton-Krylov method is especially attractive for simulating circuits with a large amount of parasitic RLC elements for post-layout verification. |
| Slides (pdf file) | 4C-1 |
4C-2
| Title | An Efficient and Globally Convergent Homotopy Method for Finding DC Operating Points of Nonlinear Circuits |
| Author | *Kiyotaka Yamamura, Wataru Kuroki (Chuo University, Japan) |
| Abstract | Finding DC operating points of nonlinear circuits is an important problem in circuit simulation. The Newton-Raphson method employed in SPICE-like simulators often fails to converge to a solution. To overcome this convergence problem, homotopy methods have been studied from various viewpoints. There are several types of homotopy methods, one of which succeeded in solving bipolar analog circuits with more than 20000 elements with the theoretical guarantee of global convergence. In this paper, we propose an improved version of the homotopy method that can find DC operating points of practical nonlinear circuits smoothly and efficiently. It is also shown that the proposed method can be easily implemented on SPICE without programming. |
| Slides (pdf file) | 4C-2 |
4C-3
| Title | Optimization of Circuit Trajectories: An Auxiliary Network Approach |
| Author | Baohua Wang, *Pinaki Mazumder (University of Michigan, United States) |
| Abstract | On optimizing circuit trajectories, i.e. continuous paths of circuit parameters, the paper presents an auxiliary network approach, which utilizes Pontryagin's Minimum Principle. Based on a set of circuit element correspondence rules, the introduced approach establishes an auxiliary network for a given circuit to be optimized, then circuit trajectories are optimized in a process of simulating the given circuit and the auxiliary network. The auxiliary network approach facilitates establishing analytic models in designing high-performance circuits that require fine tuning circuit trajectories. The paper details the theoretical framework of auxiliary network, and provides practical examples of its application in adiabatic circuit design. |
| Slides (pdf file) | No slides |
4C-4
| Title | SASIMI: Sparsity-Aware Simulation of Interconnect-Dominated Circuits with Non-Linear Devices |
| Author | *Jitesh Jain, Stephen F Cauley, Cheng-Kok Koh, Venkataramanan Balakrishnan (Purdue University, United States) |
| Abstract | We present a technique for the fast and accurate simulation of large scale VLSI interconnects with nonlinear devices, called SASIMI. The numerical efficiency of this technique is realized through linear algebraic techniques that exploit the sparsity and structure of the matrices that are encountered in VLSI structures. Numerical results show that SASIMI is up to 1400 times as fast as commercial-grade SPICE, for moderate-size circuits, with little sacrifice in simulation accuracy. |
| Slides (pdf file) | 4C-4 |
4C-5
| Title | An Unconditional Stable General Operator Splitting Method for Transistor Level Transient Analysis |
| Author | Zhengyong Zhu, Rui Shi, *Chung-Kuan Cheng (University of California, San Diego, United States), Ernest S. Kuh (University of California, Berkeley, United States) |
| Abstract | In this paper, we introduce a general operator splitting method for transient simulation of VLSI circuits. The proposed approach generates special partitions of the circuits and alternates the explicit and implicit integrations between the partitions. We prove that the method is unconditionally stable independent of the step size. The splitting scheme greatly reduces the nonzero fill-ins generated in direct methods like LU decomposition. Orders of magnitude speedup over Berkeley SPICE3 is observed for sets of circuits. |
| Slides (pdf file) | 4C-5 |