Sponsored By:
ASP-DAC 2006 Archives
5B-1
| Title | Power-Aware Scheduling and Dynamic Voltage Setting for Tasks Running on a Hard Real-Time System |
| Author | Peng Rong, *Massoud Pedram (Univ. of Southern California, United States) |
| Abstract | This paper addresses the problem of minimizing energy consumption of a computer system performing periodic hard real-time tasks with precedence constraints. In the proposed approach, dynamic power management and voltage scaling techniques are combined to reduce the energy consumption of the CPU and devices. The optimization problem is first formulated as an integer programming problem. Next, a three-phase solution framework, which integrates power management scheduling and task voltage assignment, is proposed. Experimental results show that the proposed approach outperforms existing methods by an average of 18% in terms of the system-wide energy savings. |
| Slides (pdf file) | 5B-1 |
5B-2
| Title | Optimal TDMA Time Slot and Cycle Length Allocation for Hard Real-Time Systems |
| Author | *Ernesto Wandeler, Lothar Thiele (ETH Zurich, Switzerland) |
| Abstract | We present an analytic method to determine the provably smallest possible slot length that must be allocated in a TDMA resource, to serve an event-triggered hard real-time load with arbitrary deterministic timing behavior. Based on this method, we then present constructive methods to find all feasible as well as the optimal cycle length in a TDMA resource, and we show how to determine the minimum required bandwidth of a TDMA resource. We demonstrate the applicability and computational efficiency of the presented methods in a case study of a large distributed embedded system with a TDMA bus, where we will find the optimal parameter set for the TDMA bus. |
| Slides (pdf file) | 5B-2 |
5B-3
| Title | POSIX modeling in SystemC |
| Author | *Hector Posadas, Jesus Adamez, Pablo Sanchez, Eugenio Villar (University of Cantabria, Spain), Francisco Blasco (DS2, Spain) |
| Abstract | Early estimation of the execution time of embedded SW is an essential task in complex, HW/SW embedded system design. Application SW execution time estimation requires taking into account the impact of the underlying RTOS. As a consequence, RTOS modeling is becoming an active research area. SystemC provides a framework for multiprocessing, HW/SW co-simulation at several abstraction levels. In this paper, a SystemC library for POSIX modeling and simulation is presented. By using the library, the SystemC specification using POSIX functions is converted automatically into a timed simulation estimating the execution time of the application SW running on the POSIX platform. The library works directly on the source code. Therefore, it provides an early and fast estimation of the performance of the system as a consequence of the architectural mapping decisions. Although accuracy is lower than when using lower-level techniques, it supports high-level design-space exploration as simulation time is significantly less than RT (ISS) simulation. |
| Slides (pdf file) | 5B-3 |
5B-4
| Title | PARLGRAN: Parallelism Granularity Selection for Scheduling Task Chains on Dynamically Reconfigurable Architectures |
| Author | *Sudarshan Banerjee, Elaheh Bozorgzadeh, Nikil Dutt (University of California, Irvine, United States) |
| Abstract | Partial dynamic reconfiguration, often called RTR (run-time reconfiguration) is a key feature in modern reconfigurable platforms. While partial RTR enables additional application performance, it imposes physical constraints necessitating simultaneous scheduling and placement while mapping application task graphs onto such architectures. In this paper we present PARLGRAN, an approach that maximizes performance of application {\it task chains} by selecting a suitable granularity of data-parallelism for individual {\it data parallel} tasks. Our approach focusses on reconfiguration delay overhead and placement-related issues (such as fragmentation) while selecting individual data-parallelism granularity as an integral part of simultaneous scheduling and placement. We demonstrate that our heuristic generates high-quality schedules on an extensive set of over a 1000 synthetic experiments by comparing the results with an approach that tries to statically maximize data-parallelism, i.e., does not consider the overheads and constraints associated with partial RTR. A detailed case-study on JPEG encoding additionally confirms that blindly maximizing data-parallelism can result in schedules even worse than that generated by a simple (but RTR-aware) approach oblivious to data-parallelism. |
| Slides (pdf file) | 5B-4 |
5B-5
| Title | Memory Optimal Single Appearance Schedule with Dynamic Loop Count for Synchronous Dataflow Graphs |
| Author | *Hyunok Oh, Nikil Dutt (University of California, Irvine, United States), Soonhoi Ha (Seoul National University, Republic of Korea) |
| Abstract | In this paper, we propose a new single appearance schedule for synchronous dataflow programs to minimize data memory and code memory size simultaneously. While a single appearance schedule promises only one appearance of each node definition in the generated code, it requires significant amount of data memory overhead compared with a buffer optimal schedule allowing multiple appearance. The key idea of the proposed technique is to make a dynamic decision of loop count to make a schedule quasi-static. The proposed quasi-static schedule produces a single appearance schedule code with minimum data memory requirement. We prove that every buffer optimal schedule can be transformed to our single appearance schedule which requires optimal buffer size for arbitrary synchronous dataflow graphs.The only penalty for the proposed technique is slight performance overhead of computing loop counts dynamically. In order to minimize the overhead we propose optimization techniques. Experimental results show that the proposed algorithm reduces 20% total memory with less than 1% performance overhead compared with the previous single appearance schedule algorithms. |
| Slides (pdf file) | 5B-5 |