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ASP-DAC 2006 Archives
5D-1
| Title | Low-Power Design Methodology for Module-wise Dynamic Voltage and Frequency Scaling with Dynamic De-skewing Systems |
| Author | *Takeshi Kitahara, Hiroyuki Hara, Shinichiro Shiratake (Toshiba Corporation Semiconductor Company, Japan), Yoshiki Tsukiboshi (Toshiba Microelectronics Corporation, Japan), Tomoyuki Yoda, Tetsuaki Utsumi, Fumihiro Minami (Toshiba Corporation Semiconductor Company, Japan) |
| Abstract | This paper discusses design methodology for a module-wise dynamic voltage and frequency scaling(DVFS) technique. We propose a novel clock design methodology to minimize the inter-module clock skew for solving one of the major design issues in the module-wise DVFS. We also describe a method of determining the minimum supply voltage value for a module. Our experimental results show that the module-wise DVFS can reduce 53% power compared with the chip-wise DVFS, and 17% more reduction was achieved by applying the minimum supply voltage proposed. |
| Slides (pdf file) | 5D-1 |
5D-2
| Title | Single-Chip Multi-Processor Integrating Quadruple 8-Way VLIW Processors with Interface Timing Analysis Considering Power Supply Noise |
| Author | *Satoshi Imai, Atsuki Inoue, Motoaki Matsumura, Kenichi Kawasaki, Atsuhiro Suga (Fujitsu Lab., Japan) |
| Abstract | This paper introduces a 51.2Gops, 1.0GB/s-DMA single-chip multi-processor integrating quadruple cores and proposes a new power integrity analysis. Our multi-processor is designed to decode MP@HL streams without any dedicated circuits. To achieve such high performance, data throughput as well as processing capability is important, requiring a large number of high speed I/Os. However, this makes for a high level of power supply noise. We then applied an interface timing margin analysis tool that took power supply noise into account, and succeeded in putting reasonable restrictions on LSI design, as well as that for the printed circuit board. As a result, we succeeded in operating the processor at 533MHz with the 2ch 64bit main memory IF at 266MHz and 64bit system bus at 178MHz. |
| Slides (pdf file) | 5D-2 |
5D-3
| Title | A System-level Power-estimation Methodology based on IP-level Modeling, Power-level Adjustment, and Power Accumulation |
| Author | *Masafumi Onouchi, Tetsuya Yamada (Hitachi Ltd., Japan), Kimihiro Morikawa, Isamu Mochizuki, Hidetoshi Sekine (Renesas Technology Corp., Japan) |
| Abstract | We have developed a specialized rapid power-estimation methodology for multimedia applications. For a multimedia application, we developed three methodologies: an IP-level modeling a power-level adjustment and a power accumulation methodologies. With these methodologies, the system-level power estimation becomes so precise and easy that we can revise the SoC design to reduce its power. According to a comparison of the system-level power estimated with these methodologies to board-measured power, the error between the two powers is less than 5.6%. |
| Slides (pdf file) | 5D-3 |
5D-4
| Title | PowerViP: SoC Power Estimation Framework at Transaction Level |
| Author | *Ikhwan Lee, Hyunsuk Kim, Peng Yang, Sungjoo Yoo (Samsung Electronics, Co. Ltd., Republic of Korea), Eui-Young Chung (Yonsei University, Republic of Korea), Kyu-Myung Choi, Jeong-Taek Kong, Soo-Kwan Eo (Samsung Electronics, Co. Ltd., Republic of Korea) |
| Abstract | In this work, we propose a SoC power estimation framework built on our system-level simulation environment. Our framework provides designers with the system-level power profile in a cycle-accurate manner. We target the framework to run fast and accurately, which is enabled by adopting different modeling techniques depending on the power characteristics of various IP blocks. The framework can be applied to any target SoC design. |
| Slides (pdf file) | 5D-4 |