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ASP-DAC 2006 Archives
8D-1
| Title | A New Test and Characterization Scheme for 10+ GHz Low Jitter Wide Band PLL |
| Author | *Kazuhiko Miki (Toshiba Corporation, Japan), David Boerstler, Eskinder Hailu, Jieming Qi, Sarah Pettengill (IBM Microelectronics, United States), Yuichi Goto (Toshiba Corporation, Japan) |
| Abstract | This paper presents a new test and characterization scheme for 10+ GHz low jitter wide band PLL in 90 nm partially depleted (PD) Silicon-On-Insulator (SOI) CMOS technology. We measure the frequency range of VCOs without adding any devices for test between charge-pump (CP) and voltage- controlled oscillator (VCO). That test scheme gives us the intermediate frequency of VCO as well as the maximum and the minimum frequency. This paper also describes circuitry to observe the duty cycle of 4.2GHz clock directly on a wafer probe station, including a method to verify the measured duty cycle. |
| Slides (pdf file) | 8D-1 |
8D-2
| Title | An SPU Reference Model for Simulation, Random Test Generation and Verification |
| Author | *Yukio Watanabe (Toshiba Corporation Semiconductor Company, Japan), Balazs Sallay, Brad Michael, Daniel Brokenshire, Gavin Meil, Hazim Shafi (IBM, United States), Daisuke Hiraoka (Sony Computer Entertainment Inc., Japan) |
| Abstract | An instruction set level reference model was developed for the Synergistic Processing Unit development. This reference model was used for the simulators, the test case generator, the verification environment and the software development. Using the same reference model for multiple purposes made it easier to keep up with the architecture changes. Also including the reference model in the simulation environment increased the robustness for the random test executions to find bugs that are usually difficult to catch. |
| Slides (pdf file) | 8D-2 |
8D-3
| Title | A Cycle Accurate Power Estimation Tool |
| Author | *Rajat Chaudhry, Daniel Stasiak, Stephen Posluszny, Sang Dhong (IBM Corporation, United States) |
| Abstract | Power consumption is one of the major challenges in VLSI Design. Power constrained designs need tools to accurately predict the power consumption and provide feedback to designers on the efficiency of the power management logic. In this paper we present the methodology behind a cycle accurate power estimation tool. This tool was used to estimate the power of a first generation CELL Processor. The tool extracts switching and clock activity from RTL simulations and applies them to transistor level macro power models to calculate the power for every cycle of the simulation trace. |
| Slides (pdf file) | 8D-3 |
8D-4
| Title | Key Features of the Design Methodology Enabling a Multi-Core SoC Implementation of a First-Generation CELL Processor |
| Author | *Dac Pham, Hans-Werner Anderson, Erwin Behnen, Mark Bolliger, Sanjay Gupta, Peter Hofstee, Paul Harvey, Charles Johns, Jim Kahle (IBM, United States), Atsushi Kameyama (Toshiba America Electronic Components, United States), John Keaty, Bob Le, Sang Lee, Tuyen Nguyen, John Petrovick, Mydung Pham, Juergen Pille, Stephen Posluszny, Mack Riley, Joseph Verock, James Warnock, Steve Weitzel, Dieter Wendel (IBM, United States) |
| Abstract | This paper reviews the design challenges that current and future processors must face, with stringent power limits and high frequency targets, and the design methods required to overcome the above challenges and address the continuing Giga-scale system integration trend. This paper then describes the details behind the design methodology that was used to successfully implement a first-generation CELL processor - a multi-core SoC. Key features of this methodology are broad optimization with fast rule-based analysis engines using macro-level abstraction for constraints propagation up/down the design hierarchy, coupled with accurate transistor level simulation for detailed analysis. The methodology fostered the modular design concept that is inherent to the CELL architecture, enabling a high frequency design by maximizing custom circuit content through re-use, and balanced power, frequency, and die size targets through global convergence capabilities. The design has roughly 241 million transistors implemented in 90nm SOI technology with 8 levels of copper interconnects and one local interconnect layer. The chip has been tested at various temperatures, voltages, and frequencies. Correct operation has been observed in the lab on first pass silicon at frequencies well over 4GHz. |
| Slides (pdf file) | 8D-4 |