Technical Program Committee
Technical Program Chair
- Hidetoshi Onodera (Kyoto University)
Technical Program Vice Chair
- Yusuke Matsunaga (Kyushu University)
Secretary
- Masanori Hashimoto (Osaka University)
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Subcommittees and subcommittee chairs
* : Subcommittee Chairs
1) System Level Design Methodology
- Youn-Long Lin (National Tsing Hua University) *
- Soonhoi Ha (Seoul National University)
- Ahmed Jerraya (TIMA)
- Tsuneo Nakata (Fujitsu Laboratories)
- Yoshinori Takeuchi (Osaka University)
2) Embedded and Real-Time Systems
- Hiroyuki Tomiyama (Nagoya University) *
- Pai Chou (University of California, Irvine)
- Tei-Wei Kuo (National Taiwan University)
- Sri Parameswaran (University of New South Wales)
- Sungjoo Yoo (Samsung)
3) Behavioral/Logic Synthesis and Optimization
- Kiyoung Choi (Seoul National University) *
- Shih-Chieh Chang (National Tsing Hua University)
- Shinji Kimura (Waseda University)
- Diana Marculescu (Carnegie Mellon University)
- Shigeru Yamashita (AIST Nara)
4) Validation and Verification for Behavioral/Logic Design
- Kiyoharu Hamaguchi (Osaka University) *
- Jin-Young Choi (Korea University)
- Shin'ichi Minato (Hokkaido University)
- Karem Sakallah (University of Michigan)
- Farn Wang (National Taiwan University)
5) Physical Design (Routing)
Martin D. F. Wong (University of Illinois, Urbana-Champaign) *
- Tong Jing (Tsinghua University)
- Youichi Shiraishi (Gunma University)
- Atsushi Takahashi (Tokyo Institute of Technology)
- Ting-Chi Wang (National Tsing Hua University)
6) Physical Design (Placement)
Shin'ichi Wakabayashi (Hiroshima City University) *
- Yao-Wen Chang (National Taiwan University)
- Jason Cong (University of California, Los Angeles)
- Shigetoshi Nakatake (University of Kitakyushu)
- Evangeline F.Y. Young (Chinese University of Hong Kong)
7) Timing, Power, Signal/Power Integrity Analysis and Optimization
- Sachin Sapatnekar (University of Minnesota) *
- Shabbir Batterywala (Synopsys, India)
- Jin-Jia Liou (National Taiwan University)
- Takashi Sato (Renesas)
- Weiping Shi (Texas A&M University)
- Youngsoo Shin (KAIST)
- Sheldon Tan (University of California, Riverside)
- Ryuichi Yamaguchi (Matsushita)
8) Interconnect, Device and Circuit Modeling and Simulation
- Hideki Asai (Shizuoka University) *
- Arun Chandrasekhar (Intel, India)
- Charlie Chung-Ping Chen (National Taiwan University)
- Eli Chiprout (Intel)
- Yungseon Eo (Hanyang University)
- Hiroo Masuda (STARC)
- Jae-Kyung Wee (Soongsil University)
9) Test and Design for Testability
- Seiji Kajihara (Kyushu Institute of Technology) *
- Masaki Hashizume (Tokushima University)
- Sungho Kang (Yonsei University)
- XiaoWei Li (China Academy of Sciences)
- Prab Varma (Veritable)
10) Analog, RF and Mixed Signal Design and CAD
- Makoto Nagata (Kobe University) *
- Seijiro Moriyama (PDF Solutions, Japan)
- Hong-June Park (POSTECH)
- Jaijeet Roychowdhury (University of Minnesota)
- Chau-Chin Su (National Chao-Tung University)
11) Leading Edge Design Methodology for SOCs ans SIPs
- Hideharu Amano (Keio University) *
- Ing-Jer Huang (National Sun-Yat-Sen University)
- Satoshi Matsushita (NEC)
- Borivoje Nikolic (University of California, Berkeley)
- In-Cheol Park (KAIST)
- Yulu Yang (Nankai University)
