| Wednesday January 25, 2006 |
| Title | Robust Analytical Gate Delay Modeling for Low Voltage Circuits |
| Author | Anand Ramalingam (Univ. of Texas, Austin, United States), Sreekumar V. Kodakara (Univ. of Minnesota, United States), Anirudh Devgan (Magma, United States), *David Z. Pan (Univ. of Texas, Austin, United States) |
| Page | pp. 61 - 66 |
| Detailed information (abstract, keywords, etc) | |
| Title | CGTA: Current Gain-based Timing Analysis for Logic Cells |
| Author | Shahin Nazarian, *Massoud Pedram (Univ. of Southern California, United States), Tao Lin, Emre Tuncer (Magma, United States) |
| Page | pp. 67 - 72 |
| Detailed information (abstract, keywords, etc) | |
| Title | Efficient Static Timing Analysis Using a Unified Framework for False Paths and Multi-Cycle Paths |
| Author | Shuo Zhou, Bo Yao, Hongyu Chen, Yi Zhu, *Chung-Kuan Cheng (Univ. of California, San Diego, United States), Mike Hutton (Altera Corp., United States) |
| Page | pp. 73 - 78 |
| Detailed information (abstract, keywords, etc) | |
| Title | Crosstalk Analysis using Reconvergence Correlation |
| Author | *Sachin Shrivastava, Rajendra Pratap, Harindranath Parameswaran, Manuj Verma (Cadence Design Systems, India) |
| Page | pp. 79 - 83 |
| Detailed information (abstract, keywords, etc) | |
| Title | Process-Induced Skew Reduction in Nominal Zero-Skew Clock Trees |
| Author | *Matthew R. Guthaus, Dennis Sylvester (Univ. of Michigan, United States), Richard B. Brown (Univ. of Utah, United States) |
| Page | pp. 84 - 89 |
| Detailed information (abstract, keywords, etc) | |