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The 11th Asia and South Pacific Design Automation Conference

Wednesday January 25, 2006

Session 1D University Design Contest (10:15 - 12:20)
Location: Room 416+417
Chair(s): Kazutoshi Kobayashi (Kyoto University, Japan), Takahiko Arakawa (Renesas Technology, Japan)

1D-1 (Time: 10:15 - 10:20)
TitleA Low Dynamic Power and Low Leakage Power 90-nm CMOS Square-Root Circuit
Author*Tadayoshi Enomoto, Nobuaki Kobayashi (Chuo University, Japan)
Pagepp. 90 - 91
Keyworddynamic power, leakage power, square-root, CMOS, 90 nm
AbstractTo drastically reduce the dynamic power (PAT) and the leakage power (PST), while to keep speed of a CMOS square-root (SR) circuit, a new algorithm, new architectures and a new leakage reduction circuit were developed. Using these techniques, a 90-nm CMOS LSI was fabricated. The PAT and PST of the new SR circuit were reduced to about 1/4 and 1/33 those of a conventional SR circuit. Measured results agreed well with simulated results.

1D-2 (Time: 10:20 - 10:25)
TitleA High-Throughput Low-Power Fully Parallel 1024-bit 1/2-Rate Low Density Parity Check Code Decoder in 3-Dimensional Integrated Circuits
AuthorLili Zhou, Cherry Wakayama, Nuttorn Jangkrajarng, Bo Hu, *Richard Shi (University of Washington, United States)
Pagepp. 92 - 93
Keywordthree-dimensional integrated circuits, LDPC decoder
AbstractA 1024-bit, -rate fully parallel low-density parity-check (LDPC) code decoder has been designed and implemented using a three-dimensional (3D) 0.18mm fully depleted silicon-on-insulator (FDSOI) CMOS technology based on wafer bonding. The taped-out 3D decoder with about 8M transistors was simulated to have a high throughput of 2Gb/s and a low power consumption of only 430mW using 6.4mm by 6.3mm of die area. The 3D implementation is estimated to offer more than 10x power-delay-area product improvement over its corresponding 2D implementation. This first large-scale 3D ASIC with fine-grain (5mm) vertical interconnects is made possible by jointly developing a complete automated 3D design flow from a commercial 2-D design flow combined with the needed 3D-design point tools.

1D-3 (Time: 10:25 - 10:30)
TitleA 16-Bit, Low-Power Microsystem with Monolithic MEMS-LC Clocking
Author*Robert M. Senger, Eric D. Marsman, Michael S. McCorquodale (University of Michigan, United States), Richard B. Brown (University of Utah, United States)
Pagepp. 94 - 95
Keywordmicrosystem, embedded system, low-power, microelectromechanical devices, LC oscillator
AbstractSingle-chip systems save the power dissipation that would be required for chip-to-chip communication, resulting in compact, low-power solutions for battery-powered applications. This paper describes the design and measured performance of a fully-functional digital core with a low-jitter, on-chip, MEMS-LC clock reference. This chip has been fabricated in TSMCs 0.18um MM/RF bulk CMOS process. Maximum power consumption of the complete microsystem is 48.78mW operating at 90MHz on a 1.8V power supply.

1D-4 (Time: 10:30 - 10:35)
TitleUltra-Low Voltage Power Management Circuit and Computation Methodology for Energy Harvesting Applications
AuthorChi-Ying Tsui, *Hui Shao, Wing-Hung Ki, Feng Su (Hong Kong University of Science and Technology, Hong Kong)
Pagepp. 96 - 97
Keywordenergy harvesting, power management, charge-triggered computation, self-time circuit
AbstractA power management and computation methodology is proposed for ultra-low power energy harvesting applications. An integrated exponential charge pump that accepts an input voltage of around 150mV and provides an unregulated output voltage of more than 1.5V serves as the power supply. To cater with the fluctuated energy source and unregulated power supply, a supply side charge-based computation methodology is proposed, of which the computation activity tracks with the fluctuation of the available energy. The idea is demonstrated in a test chip fabricated using a 0.35um technology.

1D-5 (Time: 10:35 - 10:40)
TitleA 0.5-V Sigma-Delta Modulator Using Analog T-Switch Scheme for the Subthreshold Leakage Suppression
Author*Koichi Ishida, Atit Tamtrakarn, Takayasu Sakurai (University of Tokyo, Japan)
Pagepp. 98 - 99
Keywordlow voltage, analog, sigma-delta, subthreshold leakage
AbstractA 0.5-V sigma-delta modulator implemented in a 0.15- FD-SOI process with low VTH of 0.1V using analog T-switch (AT-switch) scheme to suppress subthreshold-leakage problems is presented. The scheme is compared with the conventional circuit, which are also fabricated in the same chip. The measurement result demonstrates that the sigma-delta modulator based on AT-switch realizes 6-bit resolution through reducing non-linear leakage effects while the conventional circuit can achieve 4-bit resolution.

1D-6 (Time: 10:40 - 10:45)
TitleAn Implementation of a CMOS Down-Conversion Mixer for GSM1900 Receiver
Author*Fangqing Chu, Wei Li, Junyan Ren (Fudan University, China)
Pagepp. 100 - 101
Keywordmixer, RFIC
AbstractA 1.9-GHz down-conversion CMOS mixer, intended for the GSM1900 (PCS1900) Low-IF receivers is present with the utilization of novel folded Gilbert Cell fabricated in a RF 0.18-m CMOS process. The prototype demonstrates a good performance. It achieves a conversion gain of 6dB, SSB Noise Figure of 18.5dB and IIP3 11.5dBm while consuming 7mA current from 3.3V power supply.

1D-7 (Time: 10:45 - 10:50)
TitleIntegrated Direct Output Current Control Switching Converter using Symmetrically-Matched Self-Biased Current Sensors
Author*Yat-Hei Lam (Hong Kong University of Science and Technology, Hong Kong), Suet-Chui Koon (National Semiconductor Corporation, Hong Kong), Wing-Hung Ki, Chi-Ying Tsui (Hong Kong University of Science and Technology, Hong Kong)
Pagepp. 102 - 103
KeywordSwitching Converter, Power Electronics, Current Sensor
AbstractA non-inverting flyback converter using an integrated symmetrically-matched self-biased current sensor was fabricated in a 0.35m CMOS process. It operates in pseudo-continuous conduction mode and employs a direct output current control scheme to achieve excellent line transient response. The converter switches at 1MHz with an input of 1.2V to 2V to give an output of 1.5V and delivers 250mA.

1D-8 (Time: 10:50 - 10:55)
TitleAdaptively-Biased Capacitor-Less CMOS Low Dropout Regulator with Direct Current Feedback
Author*Yat-Hei Lam, Wing-Hung Ki, Chi-Ying Tsui (Hong Kong University of Science and Technology, Hong Kong)
Pagepp. 104 - 105
KeywordLinear Regulator, Current Sensor, low dropout regulator
AbstractA capacitor-less low dropout regulator (LDR) with direct current feedback is proposed. A symmetrically-matched voltage mirror in sensing the load current is employed, and gives an excellent line and load regulation. The dynamic biasing results in an LDR with pole-tracking that extends the bandwidth of the loop gain at high load currents. The LDR with active circuit area of 0.11mm2 was fabricated in a 0.35μm CMOS process. Measurement results demonstrated the good performance of the LDR.

1D-9 (Time: 10:55 - 11:00)
TitleA Built-in Power Supply Noise Probe for Digital LSIs
Author*Mitsuya Fukazawa, Koichiro Noguchi, Makoto Nagata, Kazuo Taki (Kobe University, Japan)
Pagepp. 106 - 107
Keywordpower supply noise, power supply integrity, on chip measurement
AbstractA design of compact noise detector circuitry that can be embedded and arrayed within a highdensity large-scale digtal circuit is demonstrated, with a prototype chip using 0.18 um CMOS technology.

1D-10 (Time: 11:00 - 11:05)
TitleA 476-gate-count Dynamic Optically Reconfigurable Gate Array VLSI chip in a standard 0.35um CMOS Technology
Author*Minoru Watanabe, Fuminori Kobayashi (Kyushu Institute of Technology, Japan)
Pagepp. 108 - 109
KeywordFPGAs, ORGAs, Optical reconfiguration, Gate Array
AbstractOptically Reconfigurable Gate Arrays (ORGAs) can easily enable both fast reconfiguration and numerous reconfiguration contexts by using an optical holographic memory and optical wide-band reconfiguration connections. Such devices present the possibility of large virtual gate-count VLSIs. This paper presents a new design of a 476-gate-count Dynamic Optically Reconfigurable Gate Array (DORGA) modified from a previously designed 68-gate-count DORGA using standard 0.35 um three-metal CMOS process technology.

1D-11 (Time: 11:05 - 11:10)
TitleMeasurement Results of Within-Die Variations on a 90nm LUT Array for Speed and Yield Enhancement of Reconfigurable Devices
Author*Kazuya Katsuki, Manabu Kotani, Kazutoshi Kobayashi, Hidetoshi Onodera (Graduate School of Informatics, Kyoto University, Japan)
Pagepp. 110 - 111
KeywordWithin-Die variations, reconfiguration
AbstractIt is possible to enhance speed and yield of reconfigurable devices utilizing WID variations. An LUT array LSI is fabricated on a 90nm process to measure WID and D2D variations. Performance fluctuations are measured by counting the number of LUTs through which a signal is passing within a certain time. D2D and WID variations are clearly observed by the measurement.

1D-12 (Time: 11:10 - 11:15)
TitleHigh-Throughput Decoder for Low-Density Parity-Check Code
Author*Tatsuyuki Ishikawa, Kazunori Shimizu, Takeshi Ikenaga, Satoshi Goto (Graduate School of Information, Production and Systems, Waseda University, Japan)
Pagepp. 112 - 113
Keywordlow-density parity-check (LDPC) codes, min-sum algorithm, partially-parallel LDPC decoder, memory-reduction
AbstractWe have designed and implemented the LDPC decoder chip with memory-reduction method to achieve high-throughput and practical chip size. The decoder decodes (3,6)-2304bit regular LDPC codes using modified min-sum algorithm. The decoder achieves a throughput of 530Mb/s at an operating frequency of 147MHz. The chip is fabricated in a 0.18um, 6 metal-layer CMOS technology. The chip size is 36mm^2.

1D-13 (Time: 11:15 - 11:20)
TitleHardware Implementation of Super Minimum All Digital FM Demodulator
Author*Nursani Rahmatullah, Arif Nugroho (Institut Teknologi Bandung, Indonesia)
Pagepp. 114 - 115
KeywordFM demodulator, new method, PLL
AbstractWe propose improvement of the new architecture of digital FM demodulator. This work enhances signal quality, system clock frequency, and superior than well known PLL technique today. No more multiplier, no more ROM or table, compact size, and very fast in transient or state response. Real implementation in Altera APEX20K200 EBC652-1X PLD gives 348 logic elements and run up to 224.42 MHz.

1D-14 (Time: 11:20 - 11:25)
TitleDesigning a Custom Architecture for DCT Using NISC Technology
AuthorBita Gorjiara, Mehrdad Reshadi, *Daniel Gajski (University of California, Irvine, United States)
Pagepp. 116 - 117
KeywordNISC, ASIP, custom processor, Discrete Cosine Transform, design exploration
AbstractThis paper presents design of a custom architecture for Discrete Cosine Transform (DCT) using No-Instruction-Set Computer (NISC) technology that is developed for fast processor customization. Using several software transformations and hardware customization, we achieved up to 10 times performance improvement, 2 times power reduction, 12.8 times energy reduction, and 3 times area reduction compared to an already-optimized soft-core MIPS implementation.

1D-15 (Time: 11:25 - 11:30)
TitleA 52mW 1200MIPS Compact DSP for Multi-Core Media SoC
Author*Shih-Hao Ou, Tay-Jyi Lin, Chao-Wei Huang, Yu-Ting Kuo, Chie-Min Chao, Chih-Wei Liu (National Chiao Tung University, Taiwan), Chein-Wei Jen (STC, ITRI, Taiwan)
Pagepp. 118 - 119
Keyworddigital signal processor, dual-core, multi-core
AbstractThis paper presents a fully-programmable DSP for multi-core media SoC, which has been optimized to execute a set of signal processing kernels very efficiently. It has a novel data-centric instruction set and the corresponding latency-insensitive micro-architecture, and is optimized concurrently with its automatic software generator. The DSP can achieve 3X performance (in cycles) of those found in commercial dual-core application processors with similar computing resources. It has been implemented in the UMC 0.18 1P6M CMOS technology and can operate at 314MHz while consuming only 52mW average power.

1D-16 (Time: 11:30 - 11:35)
TitleImplementation of H.264/AVC Decoder for Mobile Video Applications
Author*Suh Ho Lee, Ji Hwan Park, Seon Wook Kim, Sung Jea Ko, Suki Kim (Korea University, Republic of Korea)
Pagepp. 120 - 121
KeywordH.264, SoC Platform, CAVLC, IQ, IDCT, De-blocking filter
AbstractThis paper presents an H.264 baseline profile decoder based on an SOC platform design methodology. The overall decoding throughput is increased by optimized software and a dedicated hardware accelerator. We minimize the number of bus accesses and use macroblock (MB) level pipeline processing techniques to achieve a real time operation. We implemented and verified a prototype on an SOC platform with a 32-bit RISC CPU core and FPGA module. Our design can process up to 20 frames/sec with QCIF_(176x144). The proposed architecture can be easily applied to many mobile video application areas such as a digital camera and a DMB (Digital Multimedia Broadcasting) phone.

1D-17 (Time: 11:35 - 11:40)
TitleA High-Performance Platform-Based SoC for Information Security
AuthorMin Wu, Xiaoyang Zeng, *Jun Han, Yongyi Wu, Yibo Fan (State Key Lab of ASIC and System, Fudan University, China)
Pagepp. 122 - 123
KeywordPlatform-based, SoC, Information Security
AbstractA platform-based SoC named as Firebird is presented in this paper, which is used for the applications of information security. Several design aspects, which includes the embedded 32-bit RISC CPU and AMBA bus system, the reconfigurable and scalable public-key crypto-coprocessor, high-performance TRNG and several low-power schemes, make Firebird very efficient for the client-end applications of information security. Also the test results of this prototype chip indicate that Firebird can work with all these features efficiently, and has some obvious advantages over other designs in the literatures.

1D-18 (Time: 11:40 - 11:45)
TitleConfigurable Multi-Processor Architecture and its Processor Element Design
Author*Tsutomu Nishimura, Takuji Miki, Hiroaki Sugiura, Yuki Matsumoto, Masatsugu Kobayashi (Ritsumeikan University, Japan), Toshiyuki Kato, Tsutomu Eda (VLSI center, Ritsumeikan University, Japan), Hironori Yamauchi (Ritsumeikan University, Japan)
Pagepp. 124 - 125
Keywordmulti-processor system, automatic generation, hardware architecture
AbstractWe developed an application specific multi-processor generation system intended for real-time applications. In this system, we adopted a distributed memory type multi-processor architecture with hierarchical tree network as a configurable multi-processor which can be adapted to various scale systems flexibly. We have also developed a configurable multi-processor prototype as LSI chips with the 0.18 micro meter CMOS standard cell technology.

1D-19 (Time: 11:45 - 11:50)
TitleDesign and Implementation of Transducer for ARM-TMS Communication
AuthorHansu Cho, Samar Abdi, *Daniel Gajski (University of California, Irvine, United States)
Pagepp. 126 - 127
Keywordinterface design, IP reuse, communication design
AbstractCommunication between components, with different interface protocols, requires an extra component that must translate one protocol to another. This component is referred to as a transducer. In this paper we describe the design and implementation of a transducer between AMBA bus and TMS DSP bus. The transducer allows system designers to send data from AMBA compliant components to TMS compliant ones, and vice versa. The transducer was modeled in Verilog and implemented on Xilinx VirtexII FPGA board.