| Title | Fast Simulation of Large Networks of Nanotechnological and Biochemical Oscillators for Investigating Self-Organization Phenomena |
| Author | Xiaolue Lai, *Jaijeet Roychowdhury (University of Minnesota, United States) |
| Page | pp. 273 - 278 |
| Keyword | Nanoelectronics, Biochemical, Oscillator, Macromodel, Simulation |
| Abstract | We address the problem of fast and accurate computational analysis of large networks of coupled oscillators arising in nanotechnological and biochemical systems. Such systems are computationally and analytically challenging because of their very large sizes and the complex nonlinear dynamics they exhibit. We develop and apply a nonlinear oscillator macromodel that generalizes the well-known Kuramoto model for interacting oscillators, and demonstrate that using our macromodel provides important qualitative and quantitive advantages, especially for predicting self-organization phenomena such as spontaneous pattern formation. Our approach extends and applies recently-developed
computational methods for macromodelling electrical oscillators, and features both phase and amplitude components that are extracted automatically (using
numerical algorithms) from more complex differential-equation oscillator models
available in the literature. We apply our approach to networks of Tunneling Phase Logic (TPL) and Brusselator biochemical oscillators, predicting a variety
of spontaneous pattern generation phenomena. |
| Title | Newton: A Library-Based Analytical Synthesis Tool for RF-MEMS Resonators |
| Author | *Michael S. McCorquodale (Mobius Microsystems, Inc., United States), James L. McCann (Carnegie Mellon University, United States), Richard B. Brown (University of Utah, United States) |
| Page | pp. 279 - 284 |
| Keyword | MEMS, RF, Synthesis, Physical Design, Resonators |
| Abstract | Newton is a library-based CAD tool with an analytical synthesis engine which has been developed to support the direct synthesis of the physical design and an electromechanically equivalent model of RF-MEMS resonators based on process parameters and performance metrics. Newton provides accuracy comparable to finite element analysis while requiring a fraction of the computation and design time. A comparison of results from synthesis with Newton, design with FEA, and test results from fabricated devices is presented. |
| Title | A Fast Methodology for First-Time-Correct Design of PLLs Using Nonlinear Phase-Domain VCO Macromodels |
| Author | *Prashant Goyal (Indian Institute of Technology, Kanpur, India), Xiaolue Lai, Jaijeet Roychowdhury (University of Minnesota, United States) |
| Page | pp. 291 - 296 |
| Keyword | PLL, design methodology, behavioral simulation |
| Abstract | We present a novel methodology suitable for fast, correct design of modern PLLs. The central feature of
the methodology is its use of accurate, nonlinear behavioral
models for the VCO within the PLL, thus removing the
need for many time-consuming SPICE-level simulations
during the design process. We apply the new methodology
to design a novel injection-aided PLL that acquires lock
3�faster than prior designs, without trading off other
design metrics such as jitter. We demonstrate how existing
design methodologies based on behavioral simulation are
incapable of leading to our new PLL design. The nonlinear
behavioral simulations employed in our methodology are
more than 2 orders of magnitude faster than transistor-
level ones, resulting in an overall design productivity gain
of more than an order of magnitude. |
| Title | Double Edge Triggered Feedback Flip-Flop in Sub 100nm Technology |
| Author | *Seid Hadi Rasouli, Amir Amirabadi, Azam Seyedi, Ali Afzali-Kusha (University of Tehran, Iran) |
| Page | pp. 297 - 302 |
| Keyword | low power, high speed, subthreshold leakage current, flip flop |
| Abstract | In this paper, a new flip-flop called Double-edge triggered Feedback Flip-Flop (DFFF) is proposed. The dynamic power consumption of DFFF is reduced by avoiding unnecessary internal node transition. The subthreshold current in the flip-flops is very low compared to other structures. Reducing the number of transistor in the stack and increasing the number of charge path leads to higher operational speed compared to others flip-flops. The simulation results show an improvement of 44% in the speed and 45% in the static leakage power. |