| Thursday January 26, 2006 |
| Title | Low-Power Design Methodology for Module-wise Dynamic Voltage and Frequency Scaling with Dynamic De-skewing Systems |
| Author | *Takeshi Kitahara, Hiroyuki Hara, Shinichiro Shiratake (Toshiba, Japan), Yoshiki Tsukiboshi (Toshiba Microelectronics Co., Japan), Tomoyuki Yoda, Tetsuaki Utsumi, Fumihiro Minami (Toshiba, Japan) |
| Page | pp. 533 - 540 |
| Detailed information (abstract, keywords, etc) | |
| Title | Single-Chip Multi-Processor Integrating Quadruple 8-Way VLIW Processors with Interface Timing Analysis Considering Power Supply Noise |
| Author | *Satoshi Imai, Atsuki Inoue, Motoaki Matsumura, Kenichi Kawasaki, Atsuhiro Suga (Fujitsu Lab., Japan) |
| Page | pp. 541 - 546 |
| Detailed information (abstract, keywords, etc) | |
| Title | A System-level Power-estimation Methodology based on IP-level Modeling, Power-level Adjustment, and Power Accumulation |
| Author | *Masafumi Onouchi, Tetsuya Yamada (Hitachi Ltd., Japan), Kimihiro Morikawa, Isamu Mochizuki, Hidetoshi Sekine (Renesas, Japan) |
| Page | pp. 547 - 550 |
| Detailed information (abstract, keywords, etc) | |
| Title | PowerViP: SoC Power Estimation Framework at Transaction Level |
| Author | *Ikhwan Lee, Hyunsuk Kim, Peng Yang, Sungjoo Yoo (Samsung Electronics, Republic of Korea), Eui-Young Chung (Yonsei Univ., Republic of Korea), Kyu-Myung Choi, Jeong-Taek Kong, Soo-Kwan Eo (Samsung Electronics, Republic of Korea) |
| Page | pp. 551 - 558 |
| Detailed information (abstract, keywords, etc) | |