| Friday January 27, 2006 |
| Title | Fast Substrate Noise-Aware Floorplanning with Preference Directed Graph for Mixed-Signal SOCs |
| Author | *Minsik Cho, Hongjoong Shin, David Z. Pan (Univ. of Texas, Austin, United States) |
| Page | pp. 765 - 770 |
| Detailed information (abstract, keywords, etc) | |
| Title | A Fixed-die Floorplanning Algorithm Using an Analytical Approach |
| Author | *Yong Zhan, Yan Feng, Sachin S. Sapatnekar (Univ. of Minnesota, United States) |
| Page | pp. 771 - 776 |
| Detailed information (abstract, keywords, etc) | |
| Title | A Multi-Technology-Process Reticle Floorplanner and Wafer Dicing Planner for Multi-Project Wafers |
| Author | *Chien-Chang Chen, Wai-Kei Mak (National Tsing Hua Univ., Taiwan) |
| Page | pp. 777 - 782 |
| Detailed information (abstract, keywords, etc) | |
| Title | Design Space Exploration for Minimizing Multi-Project Wafer Production Cost |
| Author | Rung-Bin Lin, *Meng-Chiou Wu, Wei-Chiu Tseng, Ming-Hsine Kuo, Tsai-Ying Lin, Shr-Cheng Tsai (Yuan Ze Univ., Taiwan) |
| Page | pp. 783 - 788 |
| Detailed information (abstract, keywords, etc) | |
| Title | SAT-Based Optimal Hypergraph Partitioning with Replication |
| Author | *Michael G. Wrighton (Tabula, Inc., United States), Andre M. DeHon (California Inst. of Tech., United States) |
| Page | pp. 789 - 795 |
| Detailed information (abstract, keywords, etc) | |