| Friday January 27, 2006 |
| Title | A New Test and Characterization Scheme for 10+ GHz Low Jitter Wide Band PLL |
| Author | *Kazuhiko Miki (Toshiba, Japan), David Boerstler, Eskinder Hailu, Jieming Qi, Sarah Pettengill (IBM Microelectronics, United States), Yuichi Goto (Toshiba, Japan) |
| Page | pp. 856 - 859 |
| Detailed information (abstract, keywords, etc) | |
| Title | An SPU Reference Model for Simulation, Random Test Generation and Verification |
| Author | *Yukio Watanabe (Toshiba, Japan), Balazs Sallay, Brad Michael, Daniel Brokenshire, Gavin Meil, Hazim Shafi (IBM, United States), Daisuke Hiraoka (Sony Computer Entertainment Inc., Japan) |
| Page | pp. 860 - 866 |
| Detailed information (abstract, keywords, etc) | |
| Title | A Cycle Accurate Power Estimation Tool |
| Author | *Rajat Chaudhry, Daniel Stasiak, Stephen Posluszny, Sang Dhong (IBM, United States) |
| Page | pp. 867 - 870 |
| Detailed information (abstract, keywords, etc) | |
| Title | Key Features of the Design Methodology Enabling a Multi-Core SoC Implementation of a First-Generation CELL Processor |
| Author | *Dac Pham, Hans-Werner Anderson, Erwin Behnen, Mark Bolliger, Sanjay Gupta, Peter Hofstee, Paul Harvey, Charles Johns, Jim Kahle (IBM, United States), Atsushi Kameyama (Toshiba America Electronic Components, United States), John Keaty, Bob Le, Sang Lee, Tuyen Nguyen, John Petrovick, Mydung Pham, Juergen Pille, Stephen Posluszny, Mack Riley, Joseph Verock, James Warnock, Steve Weitzel, Dieter Wendel (IBM, United States) |
| Page | pp. 871 - 878 |
| Detailed information (abstract, keywords, etc) | |