The 11th Asia and South Pacific Design Automation Conference
Technical Program

Remark: The presenter of each paper is marked with "*".

Technical Program: SIMPLE version DETAILED version with abstract

Author Index: HERE

Session Schedule

Wednesday January 25, 2006

A	B	C	D
Op (Small Auditorium, 5F) Opening Session 8:30 - 9:00
1K (Small Auditorium, 5F) Keynote Address I 9:00 - 10:00
Break 10:00 - 10:15
1A (Room 411+412) Formal Methods for Coverage and Scalable Verification 10:15 - 12:20	1B (Room 413) Interconnect for High-End SoC 10:15 - 12:20	1C (Room 414+415) Timing Analysis and Optimization 10:15 - 12:20	1D (Room 416+417) University Design Contest 10:15 - 12:20
Lunch Break / University Design Contest Discussion at ASP-DAC Site (Room 418) 12:20 - 13:30
2A (Room 411+412) Software Techniques for Efficient SoC Design 13:30 - 15:35	2B (Room 413) Application Examples with Leading Edge Design Methodology 13:30 - 15:35	2C (Room 414+415) Placement 13:30 - 15:35	2D (Room 416+417) Special Session: Electrothermal Design of Nanoscale Integrated Circuits 13:30 - 15:35
Coffee Break (Room 418) 15:35 - 16:00
3A (Room 411+412) Logic Synthesis 16:00 - 18:05	3B (Room 413) Future Technical Directions for Design Automation 16:00 - 18:05	3C (Room 414+415) Routing and Interconnect Optimization 16:00 - 18:05	3D (Room 416+417) Special Session: Flash Memory in Embedded Systems 16:00 - 18:05

Thursday January 26, 2006

A	B	C	D
2K (Small Auditorium, 5F) Keynote Address II 9:00 - 10:00
Break 10:00 - 10:15
4A (Room 411+412) Resolving Timing Issues: Design and Test 10:15 - 12:20	4B (Room 413) Leading Edge Design Methodology for SoCs and SiPs 10:15 - 12:20	4C (Room 414+415) Advanced Circuit Simulation 10:15 - 12:20	4D (Room 416+417) Special Session: Open Access Overview 10:15 - 12:20
Lunch Break / Ph.D. Forum (Room 418) 12:20 - 13:30
5A (Room 411+412) Advances in Simulation Technologies 13:30 - 15:35	5B (Room 413) Scheduling for Embedded Systems 13:30 - 15:35	5C (Room 414+415) High Frequency Interconnect Effects in Nanometer Technology 13:30 - 15:35	5D (Small Auditorium, 5F) Designers' Forum: Low Power Design 13:30 - 15:30
Coffee Break (Room 418) 15:35 - 16:00
6A (Room 411+412) Power Optimization of Large-Scale Circuits 16:00 - 18:05	6B (Room 413) Advanced Memory and Processor Architectures for MPSoC 16:00 - 18:05	6C (Room 414+415) New Routing Techniques 16:00 - 18:05	6D (Small Auditorium, 5F) Designers' Forum Panel: 16:30 - 18:00
Banquet (Room 501+502) 18:30 - 20:30

Friday January 27, 2006

A	B	C	D
3K (Small Auditorium, 5F) Keynote Address III 9:00 - 10:00
Break 10:00 - 10:15
7A (Room 411+412) Minimization of Test Cost and Power 10:15 - 12:20	7B (Room 413) Substrate Coupling and Analog Synthesis 10:15 - 12:20	7C (Room 414+415) Statistical and Yield Analysis 10:15 - 12:20	7D (Room 416+417) Special Session: H.264/AVC Design Challenges and Solutions 10:15 - 12:20
Lunch Break 12:20 - 13:30
8A (Room 411+412) Floorplanning 13:30 - 15:35	8B (Room 413) Memory Optimization for Embedded Systems 13:30 - 15:35	8C (Room 414+415) Inductive Issues in Power Grids and Packages 13:30 - 15:35	8D (Small Auditorium, 5F) Designers' Forum: "Cell" Processor 13:30 - 15:30
Coffee Break (Room 418) 15:35 - 16:00
9A (Room 411+412) High-Level Synthesis 16:00 - 18:05	9B (Room 413) Modeling, Compilation and Optimization of Embedded Architectures 16:00 - 18:05	9C (Room 414+415) Statistical Design 16:00 - 18:05	9D (Small Auditorium, 5F) Designers' Forum Panel: 16:30 - 18:00

List of Papers

Remark: The presenter of each paper is marked with "*".

Wednesday January 25, 2006

Session Op Opening Session (8:30 - 9:00)
Location: Small Auditorium, 5F

Session 1K Keynote Address I (9:00 - 10:00)
Location: Small Auditorium, 5F
Chair(s): Fumiyasu Hirose (Cadence, Japan)

1K-1 (Time: 9:00 - 10:00)

Title	Automotive Electronics: Steady Growth for Years to Come!
Author	Alberto Sangiovanni-Vincentelli (The Edgar L. and Harold H. Buttner Chair of Electrical Engineering and Computer Science, Univ. of California, Berkeley, and Chief Technology Advisor, Member of the Board and Co-founder, Cadence Design Systems, United States)
Detailed information (abstract, keywords, etc)

Session 1A Formal Methods for Coverage and Scalable Verification (10:15 - 12:20)
Location: Room 411+412
Chair(s): Kiyoharu Hamaguchi (Osaka Univ., Japan), Valeria Bertacco (Univ. of Michigan, United States)

1A-1 (Time: 10:15 - 10:40)

Title	Transition-Based Coverage Estimation for Symbolic Model Checking
Author	*Xingwen Xu, Shinji Kimura (Waseda Univ., Japan), Kazunari Horikawa, Takehiko Tsuchiya (Toshiba, Japan)
Page	pp. 1 - 6
Detailed information (abstract, keywords, etc)

1A-2 (Time: 10:40 - 11:05)

Title	Word Level Functional Coverage Computation
Author	*Bijan Alizadeh (Microelectronic Research and Development Center of Iran, Iran)
Page	pp. 7 - 12
Detailed information (abstract, keywords, etc)

1A-3 (Time: 11:05 - 11:30)

Title	Discovering the Input Assumptions in Specification Refinement Coverage
Author	Prasenjit Basu, Sayantan Das, *Pallab Dasgupta, Partha P Chakrabarti (Indian Inst. of Tech. Kharagpur, India)
Page	pp. 13 - 18
Detailed information (abstract, keywords, etc)

1A-4 (Time: 11:30 - 11:55)

Title	Refinement Strategies for Verification Methods Based on Datapath Abstraction
Author	*Zaher Semon Andraus, Mark Hammond Liffiton, Karem Ahmad Sakallah (Univ. of Michigan, Ann Arbor, United States)
Page	pp. 19 - 24
Detailed information (abstract, keywords, etc)

1A-5 (Time: 11:55 - 12:20)

Title	Generation of Shorter Sequences for High Resolution Error Diagnosis Using Sequential SAT
Author	Sung-Jui Pan, *Kwang-Ting Cheng (Univ. of California, Santa Barbara, United States), John Moondanos, Ziyad Hanna (Intel Co., United States)
Page	pp. 25 - 29
Detailed information (abstract, keywords, etc)

Session 1B Interconnect for High-End SoC (10:15 - 12:20)
Location: Room 413
Chair(s): Yoshinori Takeuchi (Osaka Univ., Japan), Juinn-Dar Huang (National Chiao-Tung Univ., Taiwan)

1B-1 (Time: 10:15 - 10:40)

Title	Constraint-Driven Bus Matrix Synthesis for MPSoC
Author	*Sudeep Pasricha, Nikil Dutt (Univ. of California, Irvine, United States), Mohamed Ben-Romdhane (Conexant, United States)
Page	pp. 30 - 35
Detailed information (abstract, keywords, etc)

1B-2 (Time: 10:40 - 11:05)

Title	Improving Routing Efficiency for Network-on-Chip through Contention-Aware Input Selection
Author	*Dong Wu, Bashir M. Al-Hashimi, Marcus T. Schmitz (Univ. of Southampton, Great Britain)
Page	pp. 36 - 41
Detailed information (abstract, keywords, etc)

1B-3 (Time: 11:05 - 11:30)

Title	Physical Design Implementation of Segmented Buses to Reduce Communication Energy
Author	*Jin Guo, Antonis Papanikolaou, Pol Marchal, Francky Catthoor (IMEC, Belgium)
Page	pp. 42 - 47
Detailed information (abstract, keywords, etc)

1B-4 (Time: 11:30 - 11:55)

Title	Co-Synthesis of a Configurable SoC Platform based on a Network on Chip Architecture
Author	*Mário Pereira Véstias, Horácio Neto (INESC-ID, Portugal)
Page	pp. 48 - 53
Detailed information (abstract, keywords, etc)

1B-5 (Time: 11:55 - 12:20)

Title	Customized SIMD Unit Synthesis for System on Programmable Chip - A Foundation for HW/SW Partitioning with Vectorization
Author	Muhammad Omer Cheema, *Omar Hammami (ENSTA Paris, France)
Page	pp. 54 - 60
Detailed information (abstract, keywords, etc)

Session 1C Timing Analysis and Optimization (10:15 - 12:20)
Location: Room 414+415
Chair(s): Ryuichi Yamaguchi (Matsushita, Japan), Atsushi Kurokawa (STARC, Japan)

1C-1 (Time: 10:15 - 10:40)

Title	Robust Analytical Gate Delay Modeling for Low Voltage Circuits
Author	Anand Ramalingam (Univ. of Texas, Austin, United States), Sreekumar V. Kodakara (Univ. of Minnesota, United States), Anirudh Devgan (Magma, United States), *David Z. Pan (Univ. of Texas, Austin, United States)
Page	pp. 61 - 66
Detailed information (abstract, keywords, etc)

1C-2 (Time: 10:40 - 11:05)

Title	CGTA: Current Gain-based Timing Analysis for Logic Cells
Author	Shahin Nazarian, *Massoud Pedram (Univ. of Southern California, United States), Tao Lin, Emre Tuncer (Magma, United States)
Page	pp. 67 - 72
Detailed information (abstract, keywords, etc)

1C-3 (Time: 11:05 - 11:30)

Title	Efficient Static Timing Analysis Using a Unified Framework for False Paths and Multi-Cycle Paths
Author	Shuo Zhou, Bo Yao, Hongyu Chen, Yi Zhu, *Chung-Kuan Cheng (Univ. of California, San Diego, United States), Mike Hutton (Altera Corp., United States)
Page	pp. 73 - 78
Detailed information (abstract, keywords, etc)

1C-4 (Time: 11:30 - 11:55)

Title	Crosstalk Analysis using Reconvergence Correlation
Author	*Sachin Shrivastava, Rajendra Pratap, Harindranath Parameswaran, Manuj Verma (Cadence Design Systems, India)
Page	pp. 79 - 83
Detailed information (abstract, keywords, etc)

1C-5 (Time: 11:55 - 12:20)

Title	Process-Induced Skew Reduction in Nominal Zero-Skew Clock Trees
Author	*Matthew R. Guthaus, Dennis Sylvester (Univ. of Michigan, United States), Richard B. Brown (Univ. of Utah, United States)
Page	pp. 84 - 89
Detailed information (abstract, keywords, etc)

Session 1D University Design Contest (10:15 - 12:20)
Location: Room 416+417
Chair(s): Kazutoshi Kobayashi (Kyoto Univ., Japan), Takahiko Arakawa (Renesas, Japan)

1D-1 (Time: 10:15 - 10:20)

Title	A Low Dynamic Power and Low Leakage Power 90-nm CMOS Square-Root Circuit
Author	*Tadayoshi Enomoto, Nobuaki Kobayashi (Chuo Univ., Japan)
Page	pp. 90 - 91
Detailed information (abstract, keywords, etc)

1D-2 (Time: 10:20 - 10:25)

Title	A High-Throughput Low-Power Fully Parallel 1024-bit 1/2-Rate Low Density Parity Check Code Decoder in 3-Dimensional Integrated Circuits
Author	Lili Zhou, Cherry Wakayama, Nuttorn Jangkrajarng, Bo Hu, *Richard Shi (Univ. of Washington, United States)
Page	pp. 92 - 93
Detailed information (abstract, keywords, etc)

1D-3 (Time: 10:25 - 10:30)

Title	A 16-Bit, Low-Power Microsystem with Monolithic MEMS-LC Clocking
Author	*Robert M. Senger, Eric D. Marsman, Michael S. McCorquodale (Univ. of Michigan, United States), Richard B. Brown (Univ. of Utah, United States)
Page	pp. 94 - 95
Detailed information (abstract, keywords, etc)

1D-4 (Time: 10:30 - 10:35)

Title	Ultra-Low Voltage Power Management Circuit and Computation Methodology for Energy Harvesting Applications
Author	Chi-Ying Tsui, *Hui Shao, Wing-Hung Ki, Feng Su (Hong Kong Univ. of Science and Tech., Hong Kong)
Page	pp. 96 - 97
Detailed information (abstract, keywords, etc)

1D-5 (Time: 10:35 - 10:40)

Title	A 0.5-V Sigma-Delta Modulator Using Analog T-Switch Scheme for the Subthreshold Leakage Suppression
Author	*Koichi Ishida, Atit Tamtrakarn, Takayasu Sakurai (Univ. of Tokyo, Japan)
Page	pp. 98 - 99
Detailed information (abstract, keywords, etc)

1D-6 (Time: 10:40 - 10:45)

Title	An Implementation of a CMOS Down-Conversion Mixer for GSM1900 Receiver
Author	*Fangqing Chu, Wei Li, Junyan Ren (Fudan Univ., China)
Page	pp. 100 - 101
Detailed information (abstract, keywords, etc)

1D-7 (Time: 10:45 - 10:50)

Title	Integrated Direct Output Current Control Switching Converter using Symmetrically-Matched Self-Biased Current Sensors
Author	*Yat-Hei Lam (Hong Kong Univ. of Science and Tech., Hong Kong), Suet-Chui Koon (National Semiconductor Co., Hong Kong), Wing-Hung Ki, Chi-Ying Tsui (Hong Kong Univ. of Science and Tech., Hong Kong)
Page	pp. 102 - 103
Detailed information (abstract, keywords, etc)

1D-8 (Time: 10:50 - 10:55)

Title	Adaptively-Biased Capacitor-Less CMOS Low Dropout Regulator with Direct Current Feedback
Author	*Yat-Hei Lam, Wing-Hung Ki, Chi-Ying Tsui (Hong Kong Univ. of Science and Tech., Hong Kong)
Page	pp. 104 - 105
Detailed information (abstract, keywords, etc)

1D-9 (Time: 10:55 - 11:00)

Title	A Built-in Power Supply Noise Probe for Digital LSIs
Author	*Mitsuya Fukazawa, Koichiro Noguchi, Makoto Nagata, Kazuo Taki (Kobe Univ., Japan)
Page	pp. 106 - 107
Detailed information (abstract, keywords, etc)

1D-10 (Time: 11:00 - 11:05)

Title	A 476-gate-count Dynamic Optically Reconfigurable Gate Array VLSI chip in a standard 0.35um CMOS Technology
Author	*Minoru Watanabe, Fuminori Kobayashi (Kyushu Inst. of Tech., Japan)
Page	pp. 108 - 109
Detailed information (abstract, keywords, etc)

1D-11 (Time: 11:05 - 11:10)

Title	Measurement Results of Within-Die Variations on a 90nm LUT Array for Speed and Yield Enhancement of Reconfigurable Devices
Author	*Kazuya Katsuki, Manabu Kotani, Kazutoshi Kobayashi, Hidetoshi Onodera (Kyoto Univ., Japan)
Page	pp. 110 - 111
Detailed information (abstract, keywords, etc)

1D-12 (Time: 11:10 - 11:15)

Title	High-Throughput Decoder for Low-Density Parity-Check Code
Author	*Tatsuyuki Ishikawa, Kazunori Shimizu, Takeshi Ikenaga, Satoshi Goto (Waseda Univ., Japan)
Page	pp. 112 - 113
Detailed information (abstract, keywords, etc)

1D-13 (Time: 11:15 - 11:20)

Title	Hardware Implementation of Super Minimum All Digital FM Demodulator
Author	*Nursani Rahmatullah, Arif Nugroho (Institut Teknologi Bandung, Indonesia)
Page	pp. 114 - 115
Detailed information (abstract, keywords, etc)

1D-14 (Time: 11:20 - 11:25)

Title	Designing a Custom Architecture for DCT Using NISC Technology
Author	Bita Gorjiara, Mehrdad Reshadi, *Daniel Gajski (Univ. of California, Irvine, United States)
Page	pp. 116 - 117
Detailed information (abstract, keywords, etc)

1D-15 (Time: 11:25 - 11:30)

Title	A 52mW 1200MIPS Compact DSP for Multi-Core Media SoC
Author	*Shih-Hao Ou, Tay-Jyi Lin, Chao-Wei Huang, Yu-Ting Kuo, Chie-Min Chao, Chih-Wei Liu (National Chiao Tung Univ., Taiwan), Chein-Wei Jen (STC, ITRI, Taiwan)
Page	pp. 118 - 119
Detailed information (abstract, keywords, etc)

1D-16 (Time: 11:30 - 11:35)

Title	Implementation of H.264/AVC Decoder for Mobile Video Applications
Author	*Suh Ho Lee, Ji Hwan Park, Seon Wook Kim, Sung Jea Ko, Suki Kim (Korea Univ., Republic of Korea)
Page	pp. 120 - 121
Detailed information (abstract, keywords, etc)

1D-17 (Time: 11:35 - 11:40)

Title	A High-Performance Platform-Based SoC for Information Security
Author	Min Wu, Xiaoyang Zeng, *Jun Han, Yongyi Wu, Yibo Fan (Fudan Univ., China)
Page	pp. 122 - 123
Detailed information (abstract, keywords, etc)

1D-18 (Time: 11:40 - 11:45)

Title	Configurable Multi-Processor Architecture and its Processor Element Design
Author	*Tsutomu Nishimura, Takuji Miki, Hiroaki Sugiura, Yuki Matsumoto, Masatsugu Kobayashi, Toshiyuki Kato, Tsutomu Eda, Hironori Yamauchi (Ritsumeikan Univ., Japan)
Page	pp. 124 - 125
Detailed information (abstract, keywords, etc)

1D-19 (Time: 11:45 - 11:50)

Title	Design and Implementation of Transducer for ARM-TMS Communication
Author	Hansu Cho, Samar Abdi, *Daniel Gajski (Univ. of California, Irvine, United States)
Page	pp. 126 - 127
Detailed information (abstract, keywords, etc)

Session 2A Software Techniques for Efficient SoC Design (13:30 - 15:35)
Location: Room 411+412
Chair(s): Qiang Zhu (Fujitsu Lab., Japan), Ahmed Jerraya (TIMA Laboratory, France)

2A-1 (Time: 13:30 - 13:55)

Title	Energy Savings through Embedded Processing on Disk System
Author	Seung Woo Son, Guangyu Chen, Mahmut Kandemir, *Fehui Li (Pennsylvania State Univ., United States)
Page	pp. 128 - 133
Detailed information (abstract, keywords, etc)

2A-2 (Time: 13:55 - 14:20)

Title	Energy-Aware Computation Duplication for Improving Reliability in Embedded Chip Multiprocessors
Author	Guilin Chen, Mahmut Kandemir, *Feihui Li (Pennsylvania State Univ., United States)
Page	pp. 134 - 139
Detailed information (abstract, keywords, etc)

2A-3 (Time: 14:20 - 14:45)

Title	Object Duplication for Improving Reliability
Author	Guilin Chen, Guangyu Chen, *Mahmut Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin (Pennsylvania State Univ., United States)
Page	pp. 140 - 145
Detailed information (abstract, keywords, etc)

2A-4 (Time: 14:45 - 15:10)

Title	Mapping and Configuration Methods for Multi-Use-Case Networks on Chips
Author	*Srinivasan Murali (Stanford Univ., United States), Martijn Coenen, Andrei Radulescu, Kees Goossens (Philips, Netherlands), Giovanni De Micheli (EPFL, Switzerland)
Page	pp. 146 - 151
Detailed information (abstract, keywords, etc)

2A-5 (Time: 15:10 - 15:35)

Title	Conversion of Reference C Code to Dataflow Model: H.264 Encoder Case Study
Author	*Hyeyoung Hwang, Taewook Oh, Hyunuk Jung, Soonhoi Ha (Seoul National Univ., Republic of Korea)
Page	pp. 152 - 157
Detailed information (abstract, keywords, etc)

Session 2B Application Examples with Leading Edge Design Methodology (13:30 - 15:35)
Location: Room 413
Chair(s): In-Cheol Park (KAIST, Republic of Korea), Hideharu Amano (Keio Univ., Japan)

2B-1 (Time: 13:30 - 13:55)

Title	SAVS: A Self-Adaptive Variable Supply-Voltage Technique for Process -Tolerant and Power-Efficient Multi-issue Superscalar Processor Design
Author	Hai Li (Qualcomm Inc., United States), Yiran Chen (Synopsys Inc., United States), *Kaushik Roy, Cheng-Kok Koh (Purdue Univ., United States)
Page	pp. 158 - 163
Detailed information (abstract, keywords, etc)

2B-2 (Time: 13:55 - 14:20)

Title	The Design and Implementation of a Low-Latency On-Chip Network
Author	*Robert Mullins, Andrew West, Simon Moore (Univ. of Cambridge, Great Britain)
Page	pp. 164 - 169
Detailed information (abstract, keywords, etc)

2B-3 (Time: 14:20 - 14:45)

Title	A Near Optimal Deblocking Filter for H.264 Advanced Video Coding
Author	Shen-Yu Shih, Cheng-Ru Chang, *Youn-Long Lin (National Tsing Hua Univ., Taiwan)
Page	pp. 170 - 175
Detailed information (abstract, keywords, etc)

2B-4 (Time: 14:45 - 15:10)

Title	Image Segmentation and Pattern Matching Based FPGA/ASIC Implementation Architecture of Real-Time Object Tracking
Author	*Kousuke Yamaoka, Takashi Morimoto, Hidekazu Adachi, Tetsushi Koide, Hans Juergen Mattausch (Hiroshima Univ., Japan)
Page	pp. 176 - 181
Detailed information (abstract, keywords, etc)

2B-5 (Time: 15:10 - 15:35)

Title	Prefetching-Aware Cache Line Turnoff for Saving Leakage Energy
Author	*Ismail Kadayif (Canakkale Onsekiz Mart Univ., Turkey), Mahmut Kandemir, Feihui Li (Pennsylvania State Univ., United States)
Page	pp. 182 - 187
Detailed information (abstract, keywords, etc)

Session 2C Placement (13:30 - 15:35)
Location: Room 414+415
Chair(s): Evangeline F.Y. Young (Chinese Univ. of Hong Kong, Hong Kong), Shin'ichi Wakabayashi (Hiroshima City Univ., Japan)

2C-1 (Time: 13:30 - 13:55)

Title	A Robust Detailed Placement for Mixed-Size IC Designs
Author	Jason Cong, *Min Xie (Univ. of California, Los Angeles, United States)
Page	pp. 188 - 194
Detailed information (abstract, keywords, etc)

2C-2 (Time: 13:55 - 14:20)

Title	FastPlace 2.0: An Efficient Analytical Placer for Mixed-Mode Designs
Author	*Natarajan Viswanathan, Min Pan, Chris Chu (Iowa State Univ., United States)
Page	pp. 195 - 200
Detailed information (abstract, keywords, etc)

2C-3 (Time: 14:20 - 14:45)

Title	Timing-Driven Placement Based on Monotone Cell Ordering Constraints
Author	Chanseok Hwang, *Massoud Pedram (Univ. of Southern California, United States)
Page	pp. 201 - 206
Detailed information (abstract, keywords, etc)

2C-4 (Time: 14:45 - 15:10)

Title	Constraint Driven I/O Planning and Placement for Chip-package Co-design
Author	*Jinjun Xiong (Univ. of California, Los Angeles, United States), Yiu-Chung Wong, Egino Sarto (Rio Design Automation, United States), Lei He (Univ. of California, Los Angeles, United States)
Page	pp. 207 - 212
Detailed information (abstract, keywords, etc)

2C-5 (Time: 15:10 - 15:35)

Title	Simultaneous Block and I/O Buffer Floorplanning for Flip-Chip Design
Author	*Chih-Yang Peng, Wen-Chang Chao, Yao-Wen Chang (National Taiwan Univ., Taiwan), J.-H. Wang (Faraday Technology Corp., Taiwan)
Page	pp. 213 - 218
Detailed information (abstract, keywords, etc)

Session 2D Special Session: Electrothermal Design of Nanoscale Integrated Circuits (13:30 - 15:35)
Location: Room 416+417
Chair(s): Dennis Sylvester (Univ. of Michigan, United States), Mongkol Ekpanyapong (Georgia Inst. of Tech., United States)

2D-1 (Time: 13:30 - 14:00)

Title	Electrothermal Analysis and Optimization Techniques for Nanoscale Integrated Circuits
Author	*Yong Zhan, Brent Goplen, Sachin S. Sapatnekar (Univ. of Minnesota, United States)
Page	pp. 219 - 222
Detailed information (abstract, keywords, etc)

2D-2 (Time: 14:00 - 14:30)

Title	Electrothermal Engineering in the Nanometer Era: From Devices and Interconnects to Circuits and Systems
Author	*Kaustav Banerjee, Sheng-Chih Lin, Navin Srivastava (Univ. of California, Santa Barbara, United States)
Page	pp. 223 - 230
Detailed information (abstract, keywords, etc)

2D-3 (Time: 14:30 - 15:00)

Title	Area Optimization for Leakage Reduction and Thermal Stability in Nanometer Scale Technologies
Author	*Ja Chun Ku, Yehea Ismail (Northwestern Univ., United States)
Page	pp. 231 - 236
Detailed information (abstract, keywords, etc)

2D-4 (Time: 15:00 - 15:30)

Title	Compact Thermal Models for Estimation of Temperature-dependent Power/Performance in FinFET Technology
Author	Aditya Bansal, Mesut Meterelliyoz (Purdue Univ., United States), Siddharth Singh (Osmania Univerisity, India), Jung Hwan Choi, Jayathi Murthy, *Kaushik Roy (Purdue Univ., United States)
Page	pp. 237 - 242
Detailed information (abstract, keywords, etc)

Session 3A Logic Synthesis (16:00 - 18:05)
Location: Room 411+412
Chair(s): Shinji Kimura (Waseda Univ., Japan), Shih-Chieh Chang (National Tsing Hua Univ., Taiwan)

3A-1 (Time: 16:00 - 16:25)

Title	An Anytime Symmetry Detection Algorithm for ROBDDs
Author	*Neil Kettle, Andy King (Univ. of Kent, Great Britain)
Page	pp. 243 - 248
Detailed information (abstract, keywords, etc)

3A-2 (Time: 16:25 - 16:50)

Title	High Level Equivalence Symmetric Input Identification
Author	*Ming-Hong Su, Chun-Yao Wang (National Tsing Hua Univ., Taiwan)
Page	pp. 249 - 253
Detailed information (abstract, keywords, etc)

3A-3 (Time: 16:50 - 17:15)

Title	Fast Multi-Domain Clock Skew Scheduling for Peak Current Reduction
Author	*Shih-Hsu Huang, Chia-Ming Chang, Yow-Tyng Nieh (Chung Yuan Christian Univ., Taiwan)
Page	pp. 254 - 259
Detailed information (abstract, keywords, etc)

3A-4 (Time: 17:15 - 17:40)

Title	Low Area Pipelined Circuits by Multi-clock Cycle Paths and Clock Scheduling
Author	*Bakhtiar Affendi Rosdi, Atsushi Takahashi (Tokyo Inst. of Tech., Japan)
Page	pp. 260 - 265
Detailed information (abstract, keywords, etc)

3A-5 (Time: 17:40 - 18:05)

Title	A Transduction-based Framework to Synthesize RSFQ Circuits
Author	*Shigeru Yamashita (NAIST, Japan), Katsunori Tanaka (NEC, Japan), Hideyuki Takada (Kyoto Univ., Japan), Koji Obata, Kazuyoshi Takagi (Nagoya Univ., Japan)
Page	pp. 266 - 272
Detailed information (abstract, keywords, etc)

Session 3B Future Technical Directions for Design Automation (16:00 - 18:05)
Location: Room 413
Chair(s): Makoto Nagata (Kobe Univ., Japan), Ryuichi Fujimoto (Toshiba, Japan)

3B-1 (Time: 16:00 - 16:25)

Title	Fast Simulation of Large Networks of Nanotechnological and Biochemical Oscillators for Investigating Self-Organization Phenomena
Author	Xiaolue Lai, *Jaijeet Roychowdhury (Univ. of Minnesota, United States)
Page	pp. 273 - 278
Detailed information (abstract, keywords, etc)

3B-2 (Time: 16:25 - 16:50)

Title	Newton: A Library-Based Analytical Synthesis Tool for RF-MEMS Resonators
Author	*Michael S. McCorquodale (Mobius Microsystems, Inc., United States), James L. McCann (Carnegie Mellon Univ., United States), Richard B. Brown (Univ. of Utah, United States)
Page	pp. 279 - 284
Detailed information (abstract, keywords, etc)

3B-3 (Time: 16:50 - 17:15)

Title	Jitter Decomposition in Ring Oscillators
Author	*Qingqi Dou, Jacob Abraham (Univ. of Texas, Austin, United States)
Page	pp. 285 - 290
Detailed information (abstract, keywords, etc)

3B-4 (Time: 17:15 - 17:40)

Title	A Fast Methodology for First-Time-Correct Design of PLLs Using Nonlinear Phase-Domain VCO Macromodels
Author	*Prashant Goyal (Indian Inst. of Tech., Kanpur, India), Xiaolue Lai, Jaijeet Roychowdhury (Univ. of Minnesota, United States)
Page	pp. 291 - 296
Detailed information (abstract, keywords, etc)

3B-5 (Time: 17:40 - 18:05)

Title	Double Edge Triggered Feedback Flip-Flop in Sub 100nm Technology
Author	*Seid Hadi Rasouli, Amir Amirabadi, Azam Seyedi, Ali Afzali-Kusha (Univ. of Tehran, Iran)
Page	pp. 297 - 302
Detailed information (abstract, keywords, etc)

Session 3C Routing and Interconnect Optimization (16:00 - 18:05)
Location: Room 414+415
Chair(s): Youichi Shiraishi (Gunma Univ., Japan), Lei He (Univ. of California, Los Angels, United States)

3C-1 (Time: 16:00 - 16:25)

Title	Post-Routing Redundant Via Insertion for Yield/Reliability Improvement
Author	*Kuang-Yao Lee, Ting-Chi Wang (National Tsing Hua Univ., Taiwan)
Page	pp. 303 - 308
Detailed information (abstract, keywords, etc)

3C-2 (Time: 16:25 - 16:50)

Title	Temperature-Aware Routing in 3D ICs
Author	Tianpei Zhang, *Yong Zhan, Sachin S. Sapatnekar (Univ. of Minnesota, United States)
Page	pp. 309 - 314
Detailed information (abstract, keywords, etc)

3C-3 (Time: 16:50 - 17:15)

Title	Closed Form Solution for Optimal Buffer Sizing Using The Weierstrass Elliptic Function
Author	Sebastian Vogel (Darmstadt Univ. of Tech., Germany), *Martin D.F. Wong (Univ. of Illinois, Urbana-Champaign, United States)
Page	pp. 315 - 319
Detailed information (abstract, keywords, etc)

3C-4 (Time: 17:15 - 17:40)

Title	An O(mn) Time Algorithm for Optimal Buffer Insertion of Nets with m Sinks
Author	*Zhuo Robert Li, Weiping Shi (Texas A&M Univ., United States)
Page	pp. 320 - 325
Detailed information (abstract, keywords, etc)

3C-5 (Time: 17:40 - 18:05)

Title	Spec-based Flip-Flop and Latch Repeater Planning
Author	*Man Chung Hon (Intel Co., United States)
Page	pp. 326 - 331
Detailed information (abstract, keywords, etc)

Session 3D Special Session: Flash Memory in Embedded Systems (16:00 - 18:05)
Location: Room 416+417
Chair(s): Tohru Ishihara (Kyushu Univ., Japan), Hiroyuki Tomiyama (Nagoya Univ., Japan)

3D-1 (Time: 16:00 - 17:00)

Title	Current Trends in Flash Memory Technology
Author	*Sang Lyul Min, Eyee Hyun Nam (Seoul National Univ., Republic of Korea)
Page	pp. 332 - 333
Detailed information (abstract, keywords, etc)

3D-2 (Time: 17:00 - 18:00)

Title	Configurability of Performance and Overheads in Flash Management
Author	*Tei-Wei Kuo, Jen-Wei Hsieh (National Taiwan Univ., Taiwan), Li-Pin Chang (National Chiao-Tung Univ., Taiwan), Yuan-Hao Chang (National Taiwan Univ., Taiwan)
Page	pp. 334 - 341
Detailed information (abstract, keywords, etc)

Thursday January 26, 2006

Session 2K Keynote Address II (9:00 - 10:00)
Location: Small Auditorium, 5F
Chair(s): Fumiyasu Hirose (Cadence, Japan)

2K-1 (Time: 9:00 - 10:00)

Title	Challenging Device Innovation
Author	Satoru Ito (President & CEO, RENESAS Technology Corp., Japan)
Detailed information (abstract, keywords, etc)

Session 4A Resolving Timing Issues: Design and Test (10:15 - 12:20)
Location: Room 411+412
Chair(s): Masaki Hashizume (Tokushima Univ., Japan), Kazumi Hatayama (Renesas, Japan)

4A-1 (Time: 10:15 - 10:40)

Title	Delay Defect Screening for a 2.16GHz SPARC64 Microprocessor
Author	Noriyuki Ito, *Akira Kanuma, Daisuke Maruyama, Hitoshi Yamanaka, Tsuyoshi Mochizuki, Osamu Sugawara, Chihiro Endoh, Masahiro Yanagida, Takeshi Kono, Yutaka Isoda, Kazunobu Adachi, Takahisa Hiraide, Shigeru Nagasawa, Yaroku Sugiyama, Eizo Ninoi (Fujitsu, Japan)
Page	pp. 342 - 347
Detailed information (abstract, keywords, etc)

4A-2 (Time: 10:40 - 11:05)

Title	A Dynamic Test Compaction Procedure for High-quality Path Delay Testing
Author	Masayasu Fukunaga (Fujitsu, Japan), Seiji Kajihara, *Xiaoqing Wen (Kyushu Inst. of Tech., Japan), Toshiyuki Maeda, Shuji Hamada, Yasuo Sato (STARC, Japan)
Page	pp. 348 - 353
Detailed information (abstract, keywords, etc)

4A-3 (Time: 11:05 - 11:30)

Title	Delay Variation Tolerance for Domino Circuits
Author	Kai-Chiang Wu, *Cheng-Tao Hsieh, Shih-Chieh Chang (National Tsing Hua Univ., Taiwan)
Page	pp. 354 - 359
Detailed information (abstract, keywords, etc)

4A-4 (Time: 11:30 - 11:55)

Title	Efficient Identification of Multi-Cycle False Path
Author	Kai Yang, *Tim Cheng (Univ. of California, Santa Barbara, United States)
Page	pp. 360 - 365
Detailed information (abstract, keywords, etc)

4A-5 (Time: 11:55 - 12:20)

Title	IEEE Standard 1500 Compatible Interconnect Diagnosis for Delay and Crosstalk Faults
Author	*Katherine Shu-Min Li (National Chiao Tung Univ., Taiwan), Yao-Wen Chang (National Taiwan Univ., Taiwan), Chauchin Su, Chung-Len Lee (National Chiao Tung Univ., Taiwan), Jwu E Chen (National Central Univ., Taiwan)
Page	pp. 366 - 371
Detailed information (abstract, keywords, etc)

Session 4B Leading Edge Design Methodology for SoCs and SiPs (10:15 - 12:20)
Location: Room 413
Chair(s): Satoshi Matsushita (NEC, Japan), Makoto Ikeda (Univ. of Tokyo, Japan)

4B-1 (Time: 10:15 - 10:40)

Title	High-Level Architecture Exploration for MPEG4 Encoder with Custom Parameters
Author	*Marius Bonaciu, Aimen Bouchhima, Wassim Youssef, Xi Chen (TIMA Laboratory, France), Wander Cesario (MND, France), Ahmed Jerraya (TIMA Laboratory, France)
Page	pp. 372 - 377
Detailed information (abstract, keywords, etc)

4B-2 (Time: 10:40 - 11:05)

Title	Programmable Numerical Function Generators Based on Quadratic Approximation: Architecture and Synthesis Method
Author	*Shinobu Nagayama (Hiroshima City Univ., Japan), Tsutomu Sasao (Kyushu Inst. of Tech., Japan), Jon Butler (Naval Postgraduate School, United States)
Page	pp. 378 - 383
Detailed information (abstract, keywords, etc)

4B-3 (Time: 11:05 - 11:30)

Title	An Automated Design Flow for 3D Microarchitecture Evaluation
Author	*Jason Cong, Ashok Jagannathan, Yuchun Ma, Glenn Reinman, Jie Wei, Yan Zhang (Univ. of California, Los Angeles, United States)
Page	pp. 384 - 389
Detailed information (abstract, keywords, etc)

4B-4 (Time: 11:30 - 11:55)

Title	Optimal Topology Exploration for Application-Specific 3D Architectures
Author	Ozcan Ozturk, Feng Wang, *Mahmut Kandemir, Yuan Xie (Pennsylvania State Univ., United States)
Page	pp. 390 - 395
Detailed information (abstract, keywords, etc)

4B-5 (Time: 11:55 - 12:20)

Title	Task Placement Heuristic Based on 3D-Adjacency and Look-Ahead in Reconfigurable Systems
Author	Jesus Tabero (Instituto Nacional de Tecnica Aeroespacial, Spain), Julio Septien, Hortensia Mecha, *Daniel Mozos (Univ. Complutense de Madrid, Spain)
Page	pp. 396 - 401
Detailed information (abstract, keywords, etc)

Session 4C Advanced Circuit Simulation (10:15 - 12:20)
Location: Room 414+415
Chair(s): Hideki Asai (Shizuoka Univ., Japan), C.J. Richard Shi (Washington Univ., United States)

4C-1 (Time: 10:15 - 10:40)

Title	A Quasi-Newton Preconditioned Newton-Krylov Method for Robust and Efficient Time-Domain Simulation of Integrated Circuits with Strong Parasitic Couplings
Author	Zhao Li (Cadence Design Systems, United States), *Richard Shi (Univ. of Washington, United States)
Page	pp. 402 - 407
Detailed information (abstract, keywords, etc)

4C-2 (Time: 10:40 - 11:05)

Title	An Efficient and Globally Convergent Homotopy Method for Finding DC Operating Points of Nonlinear Circuits
Author	*Kiyotaka Yamamura, Wataru Kuroki (Chuo Univ., Japan)
Page	pp. 408 - 415
Detailed information (abstract, keywords, etc)

4C-3 (Time: 11:05 - 11:30)

Title	Optimization of Circuit Trajectories: An Auxiliary Network Approach
Author	Baohua Wang, *Pinaki Mazumder (Univ. of Michigan, United States)
Page	pp. 416 - 421
Detailed information (abstract, keywords, etc)

4C-4 (Time: 11:30 - 11:55)

Title	SASIMI: Sparsity-Aware Simulation of Interconnect-Dominated Circuits with Non-Linear Devices
Author	*Jitesh Jain, Stephen F Cauley, Cheng-Kok Koh, Venkataramanan Balakrishnan (Purdue Univ., United States)
Page	pp. 422 - 427
Detailed information (abstract, keywords, etc)

4C-5 (Time: 11:55 - 12:20)

Title	An Unconditional Stable General Operator Splitting Method for Transistor Level Transient Analysis
Author	Zhengyong Zhu, Rui Shi, *Chung-Kuan Cheng (Univ. of California, San Diego, United States), Ernest S. Kuh (Univ. of California, Berkeley, United States)
Page	pp. 428 - 433
Detailed information (abstract, keywords, etc)

Session 4D Special Session: Open Access Overview (10:15 - 12:20)
Location: Room 416+417
Chair(s): John Darringer (IBM, United States)

4D-1 (Time: 10:15 - 10:45)

Title	An Introduction to OpenAccess -An Open Source Data Model and API for IC Design-
Author	*Michaela Guiney, Eric Leavitt (Cadence, United States)
Page	pp. 434 - 436
Detailed information (abstract, keywords, etc)

4D-2 (Time: 10:45 - 11:15)

Title	Open Access Overview "Industrial Experience"
Author	*Yoshio Inoue (Renesas, Japan)
Page	pp. 437 - 438
Detailed information (abstract, keywords, etc)

4D-3 (Time: 11:15 - 11:45)

Title	EDA Vendor Adoption
Author	*Hillel Ofek (Sagantec, United States)
Page	p. 439
Detailed information (abstract, keywords, etc)

4D-4 (Time: 11:45 - 12:15)

Title	Utility of the OpenAccess Database in Academic Research
Author	David Papa, *Igor Markov (Univ. of Michigan, United States), Philip Chong (Cadence Design Systems, United States)
Page	pp. 440 - 441
Detailed information (abstract, keywords, etc)

Session 5A Advances in Simulation Technologies (13:30 - 15:35)
Location: Room 411+412
Chair(s): Shin'ichi Minato (Hokkaido Univ., Japan), Karem Sakallah (Univ. of Michigan, United States)

5A-1 (Time: 13:30 - 13:55)

Title	Depth-Driven Verification of Simultaneous Interfaces
Author	*Ilya Wagner, Valeria Bertacco, Todd Austin (Univ. of Michigan, United States)
Page	pp. 442 - 447
Detailed information (abstract, keywords, etc)

5A-2 (Time: 13:55 - 14:20)

Title	FSM-Based Transaction-Level Functional Coverage for Interface Compliance Verification
Author	*Man-Yun Su, Che-Hua Shih, Juinn-Dar Huang, Jing-Yang Jou (National Chiao Tung Univ., Taiwan)
Page	pp. 448 - 453
Detailed information (abstract, keywords, etc)

5A-3 (Time: 14:20 - 14:45)

Title	Hardware Debugging Method Based on Signal Transitions and Transactions
Author	*Nobuyuki Ohba, Kohji Takano (IBM Japan, Japan)
Page	pp. 454 - 459
Detailed information (abstract, keywords, etc)

5A-4 (Time: 14:45 - 15:10)

Title	Cycle Error Correction in Asynchronous Clock Modeling for Cycle-Based Simulation
Author	*Junghee Lee, Joonhwan Yi (Samsung Electronics, Republic of Korea)
Page	pp. 460 - 465
Detailed information (abstract, keywords, etc)

5A-5 (Time: 15:10 - 15:35)

Title	A Fast Logic Simulator Using a Look Up Table Cascade Emulator
Author	*Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura (Kyushu Inst. of Tech., Japan)
Page	pp. 466 - 472
Detailed information (abstract, keywords, etc)

Session 5B Scheduling for Embedded Systems (13:30 - 15:35)
Location: Room 413
Chair(s): Sri Parameswaran (Univ. of New South Wales, Australia), Sang Lyul Min (Seoul National Univ., Republic of Korea)

5B-1 (Time: 13:30 - 13:55)

Title	Power-Aware Scheduling and Dynamic Voltage Setting for Tasks Running on a Hard Real-Time System
Author	Peng Rong, *Massoud Pedram (Univ. of Southern California, United States)
Page	pp. 473 - 478
Detailed information (abstract, keywords, etc)

5B-2 (Time: 13:55 - 14:20)

Title	Optimal TDMA Time Slot and Cycle Length Allocation for Hard Real-Time Systems
Author	*Ernesto Wandeler, Lothar Thiele (ETH Zurich, Switzerland)
Page	pp. 479 - 484
Detailed information (abstract, keywords, etc)

5B-3 (Time: 14:20 - 14:45)

Title	POSIX modeling in SystemC
Author	*Hector Posadas, Jesus Adamez, Pablo Sanchez, Eugenio Villar (Univ. of Cantabria, Spain), Francisco Blasco (DS2, Spain)
Page	pp. 485 - 490
Detailed information (abstract, keywords, etc)

5B-4 (Time: 14:45 - 15:10)

Title	PARLGRAN: Parallelism Granularity Selection for Scheduling Task Chains on Dynamically Reconfigurable Architectures
Author	*Sudarshan Banerjee, Elaheh Bozorgzadeh, Nikil Dutt (Univ. of California, Irvine, United States)
Page	pp. 491 - 496
Detailed information (abstract, keywords, etc)

5B-5 (Time: 15:10 - 15:35)

Title	Memory Optimal Single Appearance Schedule with Dynamic Loop Count for Synchronous Dataflow Graphs
Author	*Hyunok Oh, Nikil Dutt (Univ. of California, Irvine, United States), Soonhoi Ha (Seoul National Univ., Republic of Korea)
Page	pp. 497 - 502
Detailed information (abstract, keywords, etc)

Session 5C High Frequency Interconnect Effects in Nanometer Technology (13:30 - 15:35)
Location: Room 414+415
Chair(s): Charlie Chung-Ping Chen (National Taiwan Univ., Taiwan), Noel Menezes (Intel, United States)

5C-1 (Time: 13:30 - 13:55)

Title	Wire Sizing with Scattering Effect for Nanoscale Interconnection
Author	Sean X. Shi, *David Z. Pan (Univ. of Texas, Austin, United States)
Page	pp. 503 - 508
Detailed information (abstract, keywords, etc)

5C-2 (Time: 13:55 - 14:20)

Title	Adaptive Admittance-based Conductor Meshing for Interconnect Analysis
Author	*Ya-Chi Yang, Cheng-Kok Koh, Venkataramanan Balakrishnan (Purdue Univ., United States)
Page	pp. 509 - 514
Detailed information (abstract, keywords, etc)

5C-3 (Time: 14:20 - 14:45)

Title	Interconnect RL Extraction at a Single Representative Frequency
Author	*Akira Tsuchiya (Kyoto Univ., Japan), Masanori Hashimoto (Osaka Univ., Japan), Hidetoshi Onodera (Kyoto Univ., Japan)
Page	pp. 515 - 520
Detailed information (abstract, keywords, etc)

5C-4 (Time: 14:45 - 15:10)

Title	An Efficient Algorithm for 3-D Reluctance Extraction Considering High Frequency Effect
Author	*Mengsheng Zhang, Wenjian Yu (Tsinghua Univ., China), Yu Du (Synopsys Inc., United States), Zeyi Wang (Tsinghua Univ., China)
Page	pp. 521 - 526
Detailed information (abstract, keywords, etc)

5C-5 (Time: 15:10 - 15:35)

Title	Macromodelling Oscillators Using Krylov-Subspace Methods
Author	Xiaolue Lai, *Jaijeet Roychowdhury (Univ. of Minnesota, United States)
Page	pp. 527 - 532
Detailed information (abstract, keywords, etc)

Session 5D Designers' Forum: Low Power Design (13:30 - 15:30)
Location: Small Auditorium, 5F
Chair(s): Haruyuki Tago (Toshiba, Japan), Makoto Ikeda (Univ. of Tokyo, Japan)

5D-1 (Time: 13:30 - 14:00)

Title	Low-Power Design Methodology for Module-wise Dynamic Voltage and Frequency Scaling with Dynamic De-skewing Systems
Author	*Takeshi Kitahara, Hiroyuki Hara, Shinichiro Shiratake (Toshiba, Japan), Yoshiki Tsukiboshi (Toshiba Microelectronics Co., Japan), Tomoyuki Yoda, Tetsuaki Utsumi, Fumihiro Minami (Toshiba, Japan)
Page	pp. 533 - 540
Detailed information (abstract, keywords, etc)

5D-2 (Time: 14:00 - 14:30)

Title	Single-Chip Multi-Processor Integrating Quadruple 8-Way VLIW Processors with Interface Timing Analysis Considering Power Supply Noise
Author	*Satoshi Imai, Atsuki Inoue, Motoaki Matsumura, Kenichi Kawasaki, Atsuhiro Suga (Fujitsu Lab., Japan)
Page	pp. 541 - 546
Detailed information (abstract, keywords, etc)

5D-3 (Time: 14:30 - 15:00)

Title	A System-level Power-estimation Methodology based on IP-level Modeling, Power-level Adjustment, and Power Accumulation
Author	*Masafumi Onouchi, Tetsuya Yamada (Hitachi Ltd., Japan), Kimihiro Morikawa, Isamu Mochizuki, Hidetoshi Sekine (Renesas, Japan)
Page	pp. 547 - 550
Detailed information (abstract, keywords, etc)

5D-4 (Time: 15:00 - 15:30)

Title	PowerViP: SoC Power Estimation Framework at Transaction Level
Author	*Ikhwan Lee, Hyunsuk Kim, Peng Yang, Sungjoo Yoo (Samsung Electronics, Republic of Korea), Eui-Young Chung (Yonsei Univ., Republic of Korea), Kyu-Myung Choi, Jeong-Taek Kong, Soo-Kwan Eo (Samsung Electronics, Republic of Korea)
Page	pp. 551 - 558
Detailed information (abstract, keywords, etc)

Session 6A Power Optimization of Large-Scale Circuits (16:00 - 18:05)
Location: Room 411+412
Chair(s): Sheldon Tan (Univ. of California, Riverside, United States), David Z. Pan (Univ. of Texas, Austin, United States)

6A-1 (Time: 16:00 - 16:25)

Title	Mathematically Assisted Adaptive Body Bias (ABB) for Temperature Compensation in Gigascale LSI Systems
Author	Sanjay V Kumar, Chris H Kim, *Sachin S Sapatnekar (Univ. of Minnesota, United States)
Page	pp. 559 - 564
Detailed information (abstract, keywords, etc)

6A-2 (Time: 16:25 - 16:50)

Title	Analysis and Optimization of Gate Leakage Current of Power Gating Circuits
Author	*Hyung-Ock Kim, Youngsoo Shin (KAIST, Republic of Korea)
Page	pp. 565 - 569
Detailed information (abstract, keywords, etc)

6A-3 (Time: 16:50 - 17:15)

Title	Delay Modeling and Static Timing Analysis for MTCMOS Circuits
Author	*Naoaki Ohkubo, Kimiyoshi Usami (Shibaura Inst. of Tech., Japan)
Page	pp. 570 - 575
Detailed information (abstract, keywords, etc)

6A-4 (Time: 17:15 - 17:40)

Title	Switching-Activity Driven Gate Sizing and Vth Assignment for Low Power Design
Author	Yu-Hui Huang, *Po-Yuan Chen, TingTing Hwang (National Tsing Hua Univ., Taiwan)
Page	pp. 576 - 581
Detailed information (abstract, keywords, etc)

6A-5 (Time: 17:40 - 18:05)

Title	Power Driven Placement with Layout Aware Supply Voltage Assignment for Voltage Island Generation in Dual-Vdd Designs
Author	*Bin Liu, Yici Cai, Qiang Zhou, Xianlong Hong (Tsinghua Univ., China)
Page	pp. 582 - 587
Detailed information (abstract, keywords, etc)

Session 6B Advanced Memory and Processor Architectures for MPSoC (16:00 - 18:05)
Location: Room 413
Chair(s): Soonhoi Ha (Seoul National Univ., Republic of Korea), Youn-Long Lin (National Tsing Hua Univ., Taiwan)

6B-1 (Time: 16:00 - 16:25)

Title	Reusable Component IP Design using Refinement-based Design Environment
Author	*Sanggyu Park, Sang-Yong Yoon, Soo-Ik Chae (Seoul National Univ., Republic of Korea)
Page	pp. 588 - 593
Detailed information (abstract, keywords, etc)

6B-2 (Time: 16:25 - 16:50)

Title	An Interface-Circuit Synthesis Method with Configurable Processor Core in IP-Based SoC Designs
Author	*Shunitsu Kohara, Naoki Tomono, Jumpei Uchida, Yuichiro Miyaoka, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ., Japan)
Page	pp. 594 - 599
Detailed information (abstract, keywords, etc)

6B-3 (Time: 16:50 - 17:15)

Title	A Real-Time and Bandwidth Guaranteed Arbitration Algorithm for SoC Bus Communication
Author	Chien-Hua Chen, *Geeng-Wei Lee, Juinn-Dar Huang, Jing-Yang Jou (National Chiao Tung Univ., Taiwan)
Page	pp. 600 - 605
Detailed information (abstract, keywords, etc)

6B-4 (Time: 17:15 - 17:40)

Title	Hierarchical Memory Size Estimation for Loop Fusion and Loop Shifting in Data-Dominated Applications
Author	*Qubo Hu (Univ. of Trondheim, Norway), Arnout Vandecappelle, Martin Palkovic (IMEC, Belgium), Per Gunnar Kjeldsberg (Univ. of Trondheim, Norway), Erik Brockmeyer, Francky Catthoor (IMEC, Belgium)
Page	pp. 606 - 611
Detailed information (abstract, keywords, etc)

6B-5 (Time: 17:40 - 18:05)

Title	A Novel Instruction Scratchpad Memory Optimization Method based on Concomitance Metric
Author	Andhi Janapsatya, Aleksandar Ignjatovic, *Sri Parameswaran (Univ. of New South Wales, Australia)
Page	pp. 612 - 617
Detailed information (abstract, keywords, etc)

Session 6C New Routing Techniques (16:00 - 18:05)
Location: Room 414+415
Chair(s): Ting-Chi Wang (National Tsing Hua Univ., Taiwan), Vijay Pitchumani (Intel, United States)

6C-1 (Time: 16:00 - 16:25)

Title	DraXRouter: Global Routing in X-Architecture with Dynamic Resource Assignment
Author	*Zhen Cao, Tong Jing (Tsinghua Univ., China), Yu Hu, Yiyu Shi (Univ. of California, Los Angeles, United States), Xianlong Hong (Tsinghua Univ., China), Xiaodong Hu, Guiying Yan (Institute of Applied Mathematics, Chinese Academy of Sciences, China)
Page	pp. 618 - 623
Detailed information (abstract, keywords, etc)

6C-2 (Time: 16:25 - 16:50)

Title	Diagonal Routing in High Performance Microprocessor Design
Author	Noriyuki Ito, Hideaki Katagiri, Ryoichi Yamashita, Hiroshi Ikeda, Hiroyuki Sugiyama, *Hiroaki Komatsu, Yoshiyasu Tanamura, Akihiko Yoshitake, Kazuhiro Nonomura, Kinya Ishizaka, Hiroaki Adachi, Yutaka Mori, Yutaka Isoda, Yaroku Sugiyama (Fujitsu, Japan)
Page	pp. 624 - 629
Detailed information (abstract, keywords, etc)

6C-3 (Time: 16:50 - 17:15)

Title	CDCTree: Novel Obstacle-Avoiding Routing Tree Construction based on Current Driven Circuit Model
Author	Yiyu Shi (Univ. of California, Los Angeles, United States), Tong Jing (Tsinghua Univ., China), *Lei He (Univ. of California, Los Angeles, United States), Zhe Feng, Xianlong Hong (Tsinghua Univ., China)
Page	pp. 630 - 635
Detailed information (abstract, keywords, etc)

6C-4 (Time: 17:15 - 17:40)

Title	A Novel Framework for Multilevel Full-Chip Gridless Routing
Author	*Tai-Chen Chen, Yao-Wen Chang (National Taiwan Univ., Taiwan), Shyh-Chang Lin (SpringSoft, Inc., Taiwan)
Page	pp. 636 - 641
Detailed information (abstract, keywords, etc)

6C-5 (Time: 17:40 - 18:05)

Title	Monotonic Parallel and Orthogonal Routing for Single-Layer Ball Grid Array Packages
Author	*Yoichi Tomioka, Atsushi Takahashi (Tokyo Inst. of Tech., Japan)
Page	pp. 642 - 647
Detailed information (abstract, keywords, etc)

Session 6D Designers' Forum Panel: (16:30 - 18:00)
Location: Small Auditorium, 5F

6D-1 (Time: 16:30 - 18:00)

Title	Functional Verification -now and future-
Author	Organizer: Haruyuki Tago (Senior Manager, TOSHIBA, Japan), Moderator: Yoshio Masubuchi (Assistant to General Manager, TOSHIBA, Japan), Panelists: Sanjay Gupta (IBM, United States), Michael Stellfox (Group Director, Cadence, United States), Tetsuji Sumioka (Senior Manager, Sony, Japan), Sunao Torii (Principal Researcher, NEC, Japan)
Detailed information (abstract, keywords, etc)

Friday January 27, 2006

Session 3K Keynote Address III (9:00 - 10:00)
Location: Small Auditorium, 5F
Chair(s): Fumiyasu Hirose (Cadence, Japan)

3K-1 (Time: 9:00 - 10:00)

Title	Effective Platform-based Development for Large-scale Systems Design
Author	Yukichi Niwa (Senior Advisory Director, Group Executive of Platform Technology Development Headquarters, CANON INC., Japan)
Detailed information (abstract, keywords, etc)

Session 7A Minimization of Test Cost and Power (10:15 - 12:20)
Location: Room 411+412
Chair(s): Seiji Kajihara (Kyushu Inst. of Tech., Japan), Satoshi Ohtake (NAIST, Japan)

7A-1 (Time: 10:15 - 10:40)

Title	A Routability Constrained Scan Chain Ordering Technique for Test Power Reduction
Author	*Xuan-Lun Huang, Jiun-Lang Huang (National Taiwan Univ., Taiwan)
Page	pp. 648 - 652
Detailed information (abstract, keywords, etc)

7A-2 (Time: 10:40 - 11:05)

Title	FCSCAN: An Efficient Multiscan-based Test Compression Technique for Test Cost Reduction
Author	*Youhua Shi, Nozomu Togawa, Shinji Kimura, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ., Japan)
Page	pp. 653 - 658
Detailed information (abstract, keywords, etc)

7A-3 (Time: 11:05 - 11:30)

Title	Compaction of Pass/Fail-based Diagnostic Test Vectors for Combinational and Sequential Circuits
Author	*Yoshinobu Higami (Ehime Univ., Japan), Kewal K. Saluja (Univ. of Wisconsin-Madison, United States), Hiroshi Takahashi, Shin-ya Kobayashi, Yuzo Takamatsu (Ehime Univ., Japan)
Page	pp. 659 - 664
Detailed information (abstract, keywords, etc)

7A-4 (Time: 11:30 - 11:55)

Title	Low-Overhead Design of Soft-Error-Tolerant Scan Flip-Flops with Enhanced-Scan Capability
Author	Ashish Goel (Purdue Univ., United States), Swarup Bhunia (Case Western Reserve Univ., United States), Hamid Mahmoodi (San Francisco State Univ., United States), *Kaushik Roy (Purdue Univ., United States)
Page	pp. 665 - 670
Detailed information (abstract, keywords, etc)

7A-5 (Time: 11:55 - 12:20)

Title	A Memory Grouping Method for Sharing Memory BIST Logic
Author	*Masahide Miyazaki, Tomokazu Yoneda, Hideo Fujiwara (NAIST, Japan)
Page	pp. 671 - 676
Detailed information (abstract, keywords, etc)

Session 7B Substrate Coupling and Analog Synthesis (10:15 - 12:20)
Location: Room 413
Chair(s): Jaijeet Roychowdhury (Univ. of Minnesota, United States), Tomohisa Kimura (Toshiba, Japan)

7B-1 (Time: 10:15 - 10:40)

Title	Equivalent Circuit Modeling of Guard Ring Structures for Evaluation of Substrate Crosstalk Isolation
Author	*Daisuke Kosaka, Makoto Nagata (Kobe Univ., Japan)
Page	pp. 677 - 682
Detailed information (abstract, keywords, etc)

7B-2 (Time: 10:40 - 11:05)

Title	A New Boundary Element Method for Accurate Modeling of Lossy Substrates with Arbitrary Doping Profiles
Author	*Xiren Wang, Wenjian Yu, Zeyi Wang (Tsinghua Univ., China)
Page	pp. 683 - 688
Detailed information (abstract, keywords, etc)

7B-3 (Time: 11:05 - 11:30)

Title	Parasitics Extraction Involving 3-D Conductors based on Multi-layered Green's Function
Author	Zuochang Ye, *Zhiping Yu (Tsinghua Univ., China)
Page	pp. 689 - 693
Detailed information (abstract, keywords, etc)

7B-4 (Time: 11:30 - 11:55)

Title	Signal-Path Driven Partition and Placement for Analog Circuit
Author	*Di Long, Xianlong Hong, Sheqin Dong (Tsinghua Univ., China)
Page	pp. 694 - 699
Detailed information (abstract, keywords, etc)

7B-5 (Time: 11:55 - 12:20)

Title	An Approach to Topology Synthesis of Analog Circuits Using Hierarchical Blocks and Symbolic Analysis
Author	*Xiaoying Wang, Lars Hedrich (Univ. of Frankfurt, Germany)
Page	pp. 700 - 705
Detailed information (abstract, keywords, etc)

Session 7C Statistical and Yield Analysis (10:15 - 12:20)
Location: Room 414+415
Chair(s): Hiroo Masuda (STARC, Japan), Seijiro Moriyama (PDF Solutions, Japan)

7C-1 (Time: 10:15 - 10:40)

Title	Statistical Corner Conditions of Interconnect Delay (Corner LPE Specifications)
Author	*Kenta Yamada, Noriaki Oda (NEC Electronics, Japan)
Page	pp. 706 - 711
Detailed information (abstract, keywords, etc)

7C-2 (Time: 10:40 - 11:05)

Title	Speed Binning Aware Design Methodology to Improve Profit under Parameter Variations
Author	Animesh Datta (Purdue Univ., United States), Swarup Bhunia (Case Western Reserve Univ., United States), Jung Hwan Choi, Saibal Mukhopadhyay, *Kaushik Roy (Purdue Univ., United States)
Page	pp. 712 - 717
Detailed information (abstract, keywords, etc)

7C-3 (Time: 11:05 - 11:30)

Title	Yield-Area Optimizations of Digital Circuits Using Non-dominated Sorting Genetic Algorithm (YOGA)
Author	Vineet Agarwal, *Janet Wang (Univ. of Arizona, United States)
Page	pp. 718 - 723
Detailed information (abstract, keywords, etc)

7C-4 (Time: 11:30 - 11:55)

Title	A Probabilistic Analysis of Pipelined Global Interconnect Under Process Variations
Author	*Navneeth Kankani, Vineet Agarwal, Janet M Wang (Univ. of Arizona, United States)
Page	pp. 724 - 729
Detailed information (abstract, keywords, etc)

7C-5 (Time: 11:55 - 12:20)

Title	Yield-Preferred Via Insertion Based on Novel Geotopological Technology
Author	Fangyi Luo (Univ. of California, Santa Cruz, United States), *Yongbo Jia (Nannor Technologies, Inc., United States), Wayne Wei-Ming Dai (Univ. of California, Santa Cruz, United States)
Page	pp. 730 - 735
Detailed information (abstract, keywords, etc)

Session 7D Special Session: H.264/AVC Design Challenges and Solutions (10:15 - 12:20)
Location: Room 416+417
Chair(s): Wayne Wolf (Princeton Univ., United States)

7D-1 (Time: 10:15 - 10:35)

Title	Introduction to H.264 Advanced Video Coding
Author	Jian-Wen Chen, Chao-Yang Kao, *Youn-Long Lin (National Tsing Hua Univ., Taiwan)
Page	pp. 736 - 741
Detailed information (abstract, keywords, etc)

7D-2 (Time: 10:35 - 10:55)

Title	Algorithms and DSP Implementation of H.264/AVC
Author	Hung-Chih Lin, Yu-Jen Wang, Kai-Ting Cheng, Shang-Yu Yeh, Wei-Nien Chen, Chia-Yang Tsai, Tian-Sheuan Chang, *Hsueh-Ming Hang (National Chiao-Tung Univ., Taiwan)
Page	pp. 742 - 749
Detailed information (abstract, keywords, etc)

7D-3 (Time: 10:55 - 11:15)

Title	Hardware Architecture Design of an H.264/AVC Video Codec
Author	Tung-Chien Chen, Chung-Jr Lian, *Liang-Gee Chen (National Taiwan Univ., Taiwan)
Page	pp. 750 - 757
Detailed information (abstract, keywords, etc)

7D-4 (Time: 11:15 - 11:35)

Title	ASIP Approach for Implementation of H.264/AVC
Author	Sung Dae Kim, Jeong Hoo Lee, Chung Jin Hyun, *Myung Hoon Sunwoo (Ajou Univ., Republic of Korea)
Page	pp. 758 - 764
Detailed information (abstract, keywords, etc)

7D-5 (Time: 11:35 - 12:15)

Title	Panel Discussion
Author	Youn-Long Lin (National Tsing Hua Univ., Taiwan), Hsueh-Ming Hang (National Chiao-Tung Univ., Taiwan), Liang-Gee Chen (National Taiwan Univ., Taiwan), Myung Hoon Sunwoo (Ajou Univ., Republic of Korea)
Detailed information (abstract, keywords, etc)

Session 8A Floorplanning (13:30 - 15:35)
Location: Room 411+412
Chair(s): Yao-Wen Chang (National Taiwan Univ., Taiwan), Shigetoshi Nakatake (Univ. of Kitakyushu, Japan)

8A-1 (Time: 13:30 - 13:55)

Title	Fast Substrate Noise-Aware Floorplanning with Preference Directed Graph for Mixed-Signal SOCs
Author	*Minsik Cho, Hongjoong Shin, David Z. Pan (Univ. of Texas, Austin, United States)
Page	pp. 765 - 770
Detailed information (abstract, keywords, etc)

8A-2 (Time: 13:55 - 14:20)

Title	A Fixed-die Floorplanning Algorithm Using an Analytical Approach
Author	*Yong Zhan, Yan Feng, Sachin S. Sapatnekar (Univ. of Minnesota, United States)
Page	pp. 771 - 776
Detailed information (abstract, keywords, etc)

8A-3 (Time: 14:20 - 14:45)

Title	A Multi-Technology-Process Reticle Floorplanner and Wafer Dicing Planner for Multi-Project Wafers
Author	*Chien-Chang Chen, Wai-Kei Mak (National Tsing Hua Univ., Taiwan)
Page	pp. 777 - 782
Detailed information (abstract, keywords, etc)

8A-4 (Time: 14:45 - 15:10)

Title	Design Space Exploration for Minimizing Multi-Project Wafer Production Cost
Author	Rung-Bin Lin, *Meng-Chiou Wu, Wei-Chiu Tseng, Ming-Hsine Kuo, Tsai-Ying Lin, Shr-Cheng Tsai (Yuan Ze Univ., Taiwan)
Page	pp. 783 - 788
Detailed information (abstract, keywords, etc)

8A-5 (Time: 15:10 - 15:35)

Title	SAT-Based Optimal Hypergraph Partitioning with Replication
Author	*Michael G. Wrighton (Tabula, Inc., United States), Andre M. DeHon (California Inst. of Tech., United States)
Page	pp. 789 - 795
Detailed information (abstract, keywords, etc)

Session 8B Memory Optimization for Embedded Systems (13:30 - 15:35)
Location: Room 413
Chair(s): Hiroyuki Tomiyama (Nagoya Univ., Japan), Preeti Ranjan Panda (Indian Inst. of Tech., Delhi, India)

8B-1 (Time: 13:30 - 13:55)

Title	Finding Optimal L1 Cache Configuration for Embedded Systems
Author	Andhi Janapsatya, Aleksandar Ignjatovic, *Sri Parameswaran (Univ. of New South Wales, Australia)
Page	pp. 796 - 801
Detailed information (abstract, keywords, etc)

8B-2 (Time: 13:55 - 14:20)

Title	Memory Size Computation for Multimedia Processing Applications
Author	Hongwei Zhu, Ilie I. Luican, *Florin Balasa (Univ. of Illinois, Chicago, United States)
Page	pp. 802 - 807
Detailed information (abstract, keywords, etc)

8B-3 (Time: 14:20 - 14:45)

Title	Maximizing Data Reuse for Minimizing Memory Space Requirements and Execution Cycles
Author	Mahmut Kandemir, Guangyu Chen, *Feihui Li (Pennsylvania State Univ., United States)
Page	pp. 808 - 813
Detailed information (abstract, keywords, etc)

8B-4 (Time: 14:45 - 15:10)

Title	Compiler-Guided Data Compression for Reducing Memory Consumption of Embedded Applications
Author	Ozcan Ozturk, Guangyu Chen, *Mahmut Kandemir (Pennsylvania State Univ., United States), Ibrahim Kolcu (Univ. of Manchester, Great Britain)
Page	pp. 814 - 819
Detailed information (abstract, keywords, etc)

8B-5 (Time: 15:10 - 15:35)

Title	Analysis of Scratch-Pad and Data-Cache Performance Using Statistical Methods
Author	*Javed Absar (IMEC, Katholieke Universiteit Leuven, Belgium), Francky Catthoor (IMEC, Belgium)
Page	pp. 820 - 825
Detailed information (abstract, keywords, etc)

Session 8C Inductive Issues in Power Grids and Packages (13:30 - 15:35)
Location: Room 414+415
Chair(s): Takashi Sato (Renesas, Japan)

8C-1 (Time: 13:30 - 13:55)

Title	Efficient Early Stage Resonance Estimation Techniques for C4 Package
Author	*Jin Shi, Yici Cai (Tsinghua Univ., China), Shelton X-D Tan (Univ. of California, Riverside, United States), Xianlong Hong (Tsinghua Univ., China)
Page	pp. 826 - 831
Detailed information (abstract, keywords, etc)

8C-2 (Time: 13:55 - 14:20)

Title	Parallel-Distributed Time-Domain Circuit Simulation of Power Distribution Networks with Frequency-Dependent Parameters
Author	*Takayuki Watanabe (Univ. of Shizuoka, Japan), Yuichi Tanji (Kagawa Univ., Japan), Hidemasa Kubota, Hideki Asai (Shizuoka Univ., Japan)
Page	pp. 832 - 837
Detailed information (abstract, keywords, etc)

8C-3 (Time: 14:20 - 14:45)

Title	Power Distribution Techniques for Dual VDD Circuits
Author	*Sarvesh Hemchandra Kulkarni, Dennis Sylvester (Univ. of Michigan, United States)
Page	pp. 838 - 843
Detailed information (abstract, keywords, etc)

8C-4 (Time: 14:45 - 15:10)

Title	Calculating Frequency-Dependent Inductance of VLSI Interconnect by Complete Multiple Reciprocity Boundary Element Method
Author	*Changhao Yan, Wenjian Yu, Zeyi Wang (Tsinghua Univ., China)
Page	pp. 844 - 849
Detailed information (abstract, keywords, etc)

8C-5 (Time: 15:10 - 15:35)

Title	Controlling Inductive Cross-talk and Power in Off-chip Buses using CODECs
Author	Brock LaMeres (Agilent Technologies Inc., United States), Kanupriya Gulati, *Sunil Khatri (Texas A&M Univ., United States)
Page	pp. 850 - 855
Detailed information (abstract, keywords, etc)

Session 8D Designers' Forum: "Cell" Processor (13:30 - 15:30)
Location: Small Auditorium, 5F
Chair(s): Haruyuki Tago (Toshiba, Japan), Makoto Ikeda (Univ. of Tokyo, Japan)

8D-1 (Time: 13:30 - 14:00)

Title	A New Test and Characterization Scheme for 10+ GHz Low Jitter Wide Band PLL
Author	*Kazuhiko Miki (Toshiba, Japan), David Boerstler, Eskinder Hailu, Jieming Qi, Sarah Pettengill (IBM Microelectronics, United States), Yuichi Goto (Toshiba, Japan)
Page	pp. 856 - 859
Detailed information (abstract, keywords, etc)

8D-2 (Time: 14:00 - 14:30)

Title	An SPU Reference Model for Simulation, Random Test Generation and Verification
Author	*Yukio Watanabe (Toshiba, Japan), Balazs Sallay, Brad Michael, Daniel Brokenshire, Gavin Meil, Hazim Shafi (IBM, United States), Daisuke Hiraoka (Sony Computer Entertainment Inc., Japan)
Page	pp. 860 - 866
Detailed information (abstract, keywords, etc)

8D-3 (Time: 14:30 - 15:00)

Title	A Cycle Accurate Power Estimation Tool
Author	*Rajat Chaudhry, Daniel Stasiak, Stephen Posluszny, Sang Dhong (IBM, United States)
Page	pp. 867 - 870
Detailed information (abstract, keywords, etc)

8D-4 (Time: 15:00 - 15:30)

Title	Key Features of the Design Methodology Enabling a Multi-Core SoC Implementation of a First-Generation CELL Processor
Author	*Dac Pham, Hans-Werner Anderson, Erwin Behnen, Mark Bolliger, Sanjay Gupta, Peter Hofstee, Paul Harvey, Charles Johns, Jim Kahle (IBM, United States), Atsushi Kameyama (Toshiba America Electronic Components, United States), John Keaty, Bob Le, Sang Lee, Tuyen Nguyen, John Petrovick, Mydung Pham, Juergen Pille, Stephen Posluszny, Mack Riley, Joseph Verock, James Warnock, Steve Weitzel, Dieter Wendel (IBM, United States)
Page	pp. 871 - 878
Detailed information (abstract, keywords, etc)

Session 9A High-Level Synthesis (16:00 - 18:05)
Location: Room 411+412
Chair(s): Shigeru Yamashita (NAIST, Japan), Youngsoo Shin (KAIST, Republic of Korea)

9A-1 (Time: 16:00 - 16:25)

Title	TAPHS: Thermal-Aware Unified Physical-Level and High-Level Synthesis
Author	*Zhenyu (Peter) Gu (Northwestern Univ., United States), Yonghong Yang (Queen's Univ., Canada), Jia Wang, Robert P. Dick (Northwestern Univ., United States), Li Shang (Queen's Univ., Canada)
Page	pp. 879 - 885
Detailed information (abstract, keywords, etc)

9A-2 (Time: 16:25 - 16:50)

Title	An Automated, Efficient and Static Bit-width Optimization Methodology Towards Maximum Bit-width-to-Error Tradeoff With Affine Arithmetic Model
Author	*Yu Pu, Yajun Ha (National Univ. of Singapore, Singapore)
Page	pp. 886 - 891
Detailed information (abstract, keywords, etc)

9A-3 (Time: 16:50 - 17:15)

Title	Abridged Addressing: A Low Power Memory Addressing Strategy
Author	*Preeti Ranjan Panda (Indian Inst. of Tech., Delhi, India)
Page	pp. 892 - 897
Detailed information (abstract, keywords, etc)

9A-4 (Time: 17:15 - 17:40)

Title	Using Speculative Computation and Parallelizing Techniques to Improve Scheduling of Control based Designs
Author	Roberto Cordone (Univ. degli studi di Crema, Italy), *Fabrizio Ferrandi, Gianluca Palermo, Marco Domenico Santambrogio, Donatella Sciuto (Politecnico di Milano, Italy)
Page	pp. 898 - 904
Detailed information (abstract, keywords, etc)

9A-5 (Time: 17:40 - 18:05)

Title	Worst Case Execution Time Analysis for Synthesized Hardware
Author	*Jun-hee Yoo, Xingguang Feng, Kiyoung Choi (Seoul National Univ., Republic of Korea), Eui-Young Chung, Kyu-Myung Choi (Samsung Electronics, Republic of Korea)
Page	pp. 905 - 910
Detailed information (abstract, keywords, etc)

Session 9B Modeling, Compilation and Optimization of Embedded Architectures (16:00 - 18:05)
Location: Room 413
Chair(s): Hiroyuki Tomiyama (Nagoya Univ., Japan), Lovic Gauthier (FLEETS, Japan)

9B-1 (Time: 16:00 - 16:25)

Title	Workload Prediction and Dynamic Voltage Scaling for MPEG Decoding
Author	Ying Tan, Parth Malani, Qinru Qiu, *Qing Wu (State Univ. of New York, Binghamton, United States)
Page	pp. 911 - 916
Detailed information (abstract, keywords, etc)

9B-2 (Time: 16:25 - 16:50)

Title	Lazy BTB: Reduce BTB Energy Consumption Using Dynamic Profiling
Author	*Yen-Jen Chang (National Chung-Hsing Univ., Taiwan)
Page	pp. 917 - 922
Detailed information (abstract, keywords, etc)

9B-3 (Time: 16:50 - 17:15)

Title	Cache Size Selection for Performance, Energy and Reliability of Time-Constrained Systems
Author	Yuan Cai (Univ. of Iowa, United States), Marcus T. Schmitz, Alireza Ejlali, Bashir M. Al-Hashimi (Univ. of Southampton, Great Britain), *Sudhakar M. Reddy (Univ. of Iowa, United States)
Page	pp. 923 - 928
Detailed information (abstract, keywords, etc)

9B-4 (Time: 17:15 - 17:40)

Title	Reducing Dynamic Compilation Overhead by Overlapping Compilation and Execution
Author	Priya Unnikrishnan (IBM Toronto, Canada), Mahmut Kandemir, *Feihui Li (Pennsylvania State Univ., United States)
Page	pp. 929 - 934
Detailed information (abstract, keywords, etc)

9B-5 (Time: 17:40 - 18:05)

Title	Functional Modeling Techniques for Efficient Sw Code Generation of Video Codec Application
Author	*Sang-Il Han (TIMA Laboratory, France), Soo-Ik Chae (Seoul National Univ., Republic of Korea), Ahmed Amine Jerraya (TIMA Laboratory, France)
Page	pp. 935 - 940
Detailed information (abstract, keywords, etc)

Session 9C Statistical Design (16:00 - 18:05)
Location: Room 414+415
Chair(s): Sachin Sapatnekar (Univ. of Minnesota, United States), Sunil Khatri (Texas A&M Univ., United States)

9C-1 (Time: 16:00 - 16:25)

Title	Convergence-Provable Statistical Timing Analysis with Level-Sensitive Latches and Feedback Loops
Author	Lizheng Zhang, Jengliang Tsai, Weijen Chen, Yuhen Hu, *Charlie Chungping Chen (Univ. of Wisconsin-Madison, United States)
Page	pp. 941 - 946
Detailed information (abstract, keywords, etc)

9C-2 (Time: 16:25 - 16:50)

Title	Parameterized Block-Based Non-Gaussian Statistical Gate Timing Analysis
Author	Soroush Abbaspour, Hanif Fatemi, *Massoud Pedram (Univ. of Southern California, United States)
Page	pp. 947 - 952
Detailed information (abstract, keywords, etc)

9C-3 (Time: 16:50 - 17:15)

Title	Statistical Leakage Minimization through Joint Selection of Gate Sizes, Gate Lengths and Threshold Voltage
Author	*Sarvesh Bhardwaj, Yu Cao, Sarma Vrudhula (Arizona State Univ., United States)
Page	pp. 953 - 958
Detailed information (abstract, keywords, etc)

9C-4 (Time: 17:15 - 17:40)

Title	Statistical Bellman-Ford Algorithm With An Application to Retiming
Author	*Mongkol Ekpanyapong (Georgia Inst. of Tech., United States), Thaisiri Watewai (Univ. of California, Berkeley, United States), Sung Kyu Lim (Georgia Inst. of Tech., United States)
Page	pp. 959 - 964
Detailed information (abstract, keywords, etc)

9C-5 (Time: 17:40 - 18:05)

Title	An Exact Algorithm for the Statistical Shortest Path Problem
Author	Liang Deng, *Martin D. F. Wong (Univ. of Illinois, Urbana-Champaign, United States)
Page	pp. 965 - 970
Detailed information (abstract, keywords, etc)

Session 9D Designers' Forum Panel: (16:30 - 18:00)
Location: Small Auditorium, 5F

9D-1 (Time: 16:30 - 18:00)

Title	Top 10 Design Issues by LSI Designers versus EDA Developers
Author	Organizer: Haruyuki Tago (Senior Manager, TOSHIBA, Japan), Moderator: Yoshiaki Hagihara (Sony Fellow, Sony, Japan), Panelists: Raul Camposano (Sr. VP&CTO, Synopsys, United States), Soo-Kwan Eo (Sr. VP, SAMSUNG, Republic of Korea), Joe Sawichi (VP, Mentor, United States), Hirofumi Taguchi (General manager, Matsushita, Japan), Yasuhiro Tani (Director, CANON, Japan), Ted Vucurevich (CTO, Cadence, Republic of Korea)
Detailed information (abstract, keywords, etc)

The 11th Asia and South Pacific Design Automation Conference Technical Program

Session Schedule

List of Papers

The 11th Asia and South Pacific Design Automation Conference
Technical Program